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| ccz 3005k central control unit edition june 28, 2000 6251-471-1pd preliminar y d a t a sheet micr onas micronas
ccz 3005k preliminary data sheet 2 micronas contents page section title 4 1. introduction 4 1.1. features 5 2. functional description 5 2.1. cpu 5 2.2. rom 5 2.3. ram 5 2.4. clock generator 6 2.5. control register 6 2.6. reset function 8 2.7. watchdog 9 2.8. ports p00 to p37 10 2.9. 6-bit dacs pwm0 to pwm5 10 2.10. 14-bit dac pwm6 11 2.11. i 2 c and im-bus interface 16 2.12. a/d converter 17 2.13. closed caption acquisition 17 2.13.1. video input 18 2.13.2. closed caption data detection 21 2.13.3. gate and window logic 25 2.14. osd 25 2.14.1. summary of osd features 25 2.14.2. fonts 25 2.14.3. osd window 26 2.14.4. colors 26 2.14.4.1. osd attribute `color' 26 2.14.4.1.1. attribute `transparent' 26 2.14.4.2. available colors 27 2.14.4.3. color palette programming 27 2.14.4.4. color palette hardware 28 2.14.5. fast blank output 28 2.14.6. half-video output 29 2.14.7. using osd 31 2.14.8. osd attributes 32 2.14.9. font definition 32 2.14.10. soft-scroll 33 2.15. cursor 33 2.15.1. cursor definition 34 2.15.2. cursor position 34 2.15.3. moving and changing the cursor 34 2.15.4. cursor control bits 35 2.15.5. cursor dma 36 2.16. h&v sync generator 38 2.17. infrared input 40 2.17.1. infrared detection status 40 2.17.2. infrared detection control 40 2.17.3. sample times ccz 3005k preliminary data sheet 3 micronas contents, continued page section title 41 2.18. timer 41 2.19. interrupt system 42 3. specifications 42 3.1. outline dimensions 42 3.2. pin connections and short descriptions 45 3.3. pin descriptions 47 3.4. pin configuration 48 3.5. pin circuits 50 3.6. electrical characteristics 50 3.6.1. absolute maximum ratings 51 3.6.2. recommended operating conditions 52 3.6.3. recommended crystal characteristics 53 3.6.4. dc characteristics 54 3.6.5. dc parameters i 2 c-bus master interface 54 3.6.6. a/d converter characteristics 55 4. definitions 55 4.1. i/o definitions 56 5. register description 74 6. appendix a: closed caption 74 6.1. the closed caption standard 74 6.1.1. data transmission format 76 6.2. closed caption decoder 76 6.2.1. operating modes 76 6.2.2. screen format 76 6.2.2.1. text mode 77 6.2.2.2. caption mode 79 6.2.3. presentation format 79 6.2.4. character format 80 6.2.5. character attributes 80 6.2.6. control codes 85 6.2.7. data rejection 85 6.2.8. automatic display enable/disable 85 6.2.8.1. enable logic and timing 85 6.2.8.2. disable logic and timing 86 7. appendix b: pin configuration of pga package 87 7.1. pin connections in cpga132f package 88 8. data sheet history ccz 3005k preliminary data sheet 4 micronas central control unit single chip microcontroller with embedded closed caption decoder 1. introduction the central control unit ccz 3005k is an integrated cir- cuit designed in cmos technology and housed in a 52-pin plastic shrink dual-in-line package. it is used as a single-chip tv controller with embedded closed cap- tion decoder and on-screen display. 1.1. features 6 mhz 65c02 cpu, 12 mhz crystal 52-pin psdip package on-chip oscillator clock generator with programmable frequency 62 kbytes internal rom 1536 bytes internal ram closed caption decoder programmable tv-line detector 2 selectable h sync inputs 2 programmable h & v sync outputs free running h & v sync generator for stable osd full-screen osd with separate 24*24 pixel cursor controls rgb and fast blank outputs color palette: 8 out of 64 different colors program- mable soft-scroll, underline, flash, italics half-video control output i 2 c/im-bus master interface six 6-bit d/a converters (pwm) single 14-bit d/a converter (pwm) for voltage synthe- sizer up to 29 port lines 8-bit a/d converter (6-bit precision) with 5 multiplexed inputs infrared input hardware supporting software decod- ing free-running timer generating interrupts power-on and clock supervision watchdog fig. 11: block diagram of the ccz 3005k pwm6 cursor 1 1 7 5 5 6 1 port 2 closed caption slicer port 3 cpu 65c02 rom ram port 0 a/d converter osd port 1 i 2 c/im-bus power on watchdog oscillator timer pwm0 to pwm5 ir in 6 6 1 1 h sync2 1 hv sync generator 2 ccz 3005k preliminary data sheet 5 micronas 2. functional description 2.1. cpu the cpu is a standard 65c02 core. 2.2. rom the ccz 3005k has 62 kbytes of mask-programmable rom on chip. it covers the addresses from 0800h to ffffh. 2.3. ram 1536 bytes ram are integrated as two portions: table 21: ram configurations page start stop length in bytes 0 and 1 0000h 01ffh 512 3 6 0300h 06ffh 1024 page 0 offers particularly fast access for the cpu and is therefore very valuable for fast, compact programs. page 1 contains the stack area. page 3 and following are used as display memory for ccd (closed caption de- coding) and osd (on-screen display). page 2 is re- served as i/o page (the 65c02 has memory-mapped i/o). 2.4. clock generator an integrated two-pin oscillator, accompanied by a pro- grammable divider, generates the clock for the microcontroller. the divider is expressed by the equa- tion f system = f xtal / 2*(n+1) where n is a value from 0 to 255. after reset n is set to 0. f system can be modified by writing a new `n' value to ad- dress 200h. important: any kind of display mode (osd or ccd) requires a system speed of f xtal/2 (n = 0). all timings in the ccz are based on f system . other timings than f system = f xtal/2 are not recommended. ???? ???? ???? ???? ???? ???? ???? fig. 21: address map page 0 page 1 page 2* page 3 page 4, 5, 6 rom ram ram ram rom i/o 0 1ffh 300h 3ffh 6ffh 0800h ffffh with the exception of addr. 02e0h to 02e7h all register addresses of page 2 are internal. with 02e0h to 02e7h external hardware ac- cess is possible. these addresses are used for emulation purposes. * ccz 3005k preliminary data sheet 6 micronas 2.5. control register this is a combination of control switches in an 8-bit reg- ister. during reset it is loaded with the contents of the address fff9h, but it can also be read and written via software (address 0201h). the switches have the fol- lowing functions: bit 0 cpu: `0' = disabled, `1' = enabled bit 1 ram; `0' = disabled, `1' = enabled 1) bit 2 rom: `0' = disabled, `1' = enabled bit 3 to 7 set them to 1 1) to use the emulator chip version: set bit 4 to `0'. this enables the additional address and data lines. if bit 1 of the control register is set to `1', ad- dresses 0 to 1ffh and 300h to 7ffh are assumed to be inside the ccz emulator chip. thus the data bus may not access external devices (ram) located in this ad- dress range. with the control byte a%11101001o = ae9ho the emulator chip can access almost 64 kbytes of exter- nal memory. only the addresses for the internal i/o reg- isters stay internal (page 2 without 2e0h to 2e7h). the logical level at the test-pin during reset decides whether the control byte is read from internal or external memory. for operation without external memory test pin = low-level is used, with the (internal) control byte set to ffh. 2.6. reset function the internal reset provides a correct basic setup of the complete hardware on the chip. an internal control regis- ter (adr. 201h) is loaded during reset with the byte out of address fff9h. the internal voltage supervision re- sets the ic if the voltage is too low. if the frequency is too low, the same function is effected by the clock supervi- sion. once activated and not refreshed correctly, the watchdog also generates a reset (see chapter 2.7. for details). these internal reset sources (watchdog, volt- age detector and clock supervision) use the reset pin as output. internal resistors limit the maximum current. osc reset + control word logic internal voltage supervision x1 x2 22 p 22 p ccz 3005k f 2 res a 0 ...a 15 reset supervision clock watchdog reset clkres resin por resout dogbit fig. 22: oscillator and reset c 1 =c 2 = i max = 10 ma 2 ccz 3005k preliminary data sheet 7 micronas normal operation fig. 23: external reset sequence v sup 123 456 fff 9 control byte int. reset f osc a 0 ...a 15 d 0 ...d 7 res 2 1 2 10 11 12 ccz 3005k preliminary data sheet 8 micronas 2.7. watchdog this counter circuit offers hardware support for software problems. it is disabled after reset and enabled with the first write of the desired time value into its register. the value to program is calculated by: (1) n = (t wd * f system / 65536) 1 with n = watchdog counter value to be programmed for t wd = the desired watchdog time and f system = system frequency. remarks: a) to prevent the generation of a areseto by the watch- dog before it could be retriggered by the software, watchdog counter values of less than 2 should not be programmed. b) the system clock as input of the watchdog counter is influenced by the system clock prescaler, determining the cpu speed (register addr. 200h). the software cannot stop this counter, but has to retrig- ger it by writing the inverted value (one's complement) of the preceding written pattern into its register, which makes unwanted retrigger loops of disturbed software unlikely. these writes have to occur within the time frame (32 ms to 2 s at 6 mhz system clock), defined with the first write. if no write with the expected pattern occurs within the programmed time period, the watchdog circuit resets the ccz at the end of the time period. the software can detect if a reset was generated by the watchdog: bit 0 of the watchdog register is `0' if the last reset was generated by the watchdog. this bit is preset (set to '1') only by power-on or writing to the watchdog register. thus checking it has to occur before the first watchdog register write access. fig. 24: watchdog 8-bit counter wd control logic internal reset clear counter 8 f system 65535 (from timer) data bus wr_wd (202h) rd_wd (202h) reset pin examples: to set a cycle time of 1 s with a 6mhz system clock, the value is 91. this value is calculated as follows: system frequency: 6mhz, watchdog cycle time: 65536 / 6mhz = 10.92ms, counter value: 1s/10.92ms = 91.55. the nearest integer value is 92. as a 0 loaded into the counter divides by 1, already, the watchdog counter has to be programmed with 92 1 = 91 . using the above-mentioned equation (1): n = 91 = 1s * 6mhz/65536 1 the software sequences in assembler could look like this: definitions: ;constants: watchdog_time equ 91 ;ccz i/oaddress: watchdog_address equ 202h ;variable: watchdog_value equ 30h ;(address of free ram ; location) example 1: during initialization the watchdog is filled with the de- sired time-value: lda #watchdog_time sta watchdog_address sta watchdog_value ; memorize pattern in the main loop of the program the watchdog has to be retriggered cyclically lda watchdog_value eor #ffh sta watchdog_address ; invert bits sta watchdog_value ; memorize new pattern example 2: if an interrupt function occurs cyclically, one value may be programmed in the interrupt service routine, while the other is written in the main loop. so both, the continuity of executing the interrupt service and the main loop are checked. during initialization the watchdog is filled with the de- sired time value: lda #watchdog_time sta watchdog_value; memorize pattern ccz 3005k preliminary data sheet 9 micronas sequence in the interrupt function: lda watchdog_value cmp #watchdog_time beq skip_irq_wd ; sta watchdog_address eor #$ff sta watchdog_value skip_irq_wd: sequence in the main loop: lda watchdog_value cmp #watchdog_time bne skip_wd ; sta watchdog_address eor #$ff sta watchdog_value skip_wd: remark: it is important to program the watchdog register with the new value before this value is memorized in the shadow variable, because this procedure could be interrupted by the interrupt which programs the watchdog with the complementary value. 2.8. ports p00 to p37 up to 29 port lines grouped in 4 ports (3 * 8bit, 1*5bit) are available: p00 to p07 8 bits p10 to p14 5 bits p20 to p27 8 bits p30 to p37 8 bits some of the port lines can be moved into the `special mode'. three registers in the i/o-page belong to each port: mode register write only (defines each line as port or special mode pin) `0' = port mode = reset value tristate register write only (disables or enables the port output stage for each line) `1' = tristate = reset value data register read/write (reads pin levels or writes port data) `0' = reset value fig. 25: port logic mode register data register special hardware tristate register wr_mode wr_data wr_tristate rd_data port pin data bus after reset all ports are in the port and the output driv- ers in the tristate mode. the port output drivers have push-pull characteristics. this may be different in the special modes (see description of special mode blocks). ccz 3005k preliminary data sheet 10 micronas 2.9. 6bit dacs pwm0 to pwm5 six digital-to-analog converters belong to the ccz 3005k. the push-pull outputs of the 6-bit pwm- converters are active if in the corresponding port regis- ters the special mode flag is set and the tristate flag is reset (output=conducting): table 22: 6bit dac ports dac port pin data register address pwm0 p20 250h pwm1 p21 251h pwm2 p22 252h pwm3 p23 253h pwm4 p24 254h pwm5 p25 255h by writing a 6-bit value to the converter's data register (d0 to d5 = value, d6, d7 = 0) the software can control the dacs. the minimum position (00h) generates a constant low output signal, the max. value (3fh) a 1/64 low signal. the clock of the pwm-converters is 1/8th of the system clock. 2.10. 14bit dac pwm6 the ccz 3005k is equipped with one 14-bit digital-to- analog converter for tuning voltage synthesis. the push- pull output of the 14-bit pwm-converter is active if in the corresponding port register the special mode flag is set and the tristate flag is reset (output=conducting): table 23: 14bit dac port dac port pin data register address pwm6 p37 256h (6 lsbs) 257h (8 msbs) by writing a 14-bit value to the converter's 2 data regis- ters the software can control the 14bit dac. the mini- mum position (0000h) generates a constant low output signal, the max. value (ff3fh) a 1/16384 low signal. writing into the msb register (257h) starts the transfer of the complete 14bit value into the internal pwm6 log- ic. this register should therefore be written after the lsb register (256h). the clock of the pwm6 converter is the system clock divided by 2. the pwm6 output needs external circuitry to generate a stable tuning voltage. fig. 26 shows the necessary components. 47k 39k 18k 10k ztk33 bf240 tuning voltage >40v pwm6 10k 10k 47 m 470p 47k 47k 470n 220n 100n 47k fig. 26: application circuit to generate tuning voltage ccz 3005k preliminary data sheet 11 micronas 2.11. i 2 c and im-bus interface in special mode (conducting), port 1 works as a master bus interface. it can generate two different kinds of for- mat: i 2 c format im format two terminals are available: 3 pins (special mode of p12 to p14) as im or i 2 c lines and 2 pins (special mode of p10, p11) as i 2 c. terminal 2 can only operate as i 2 c in- terface because of the missing third line. the msbit of the bus prescaler registers (address 2dbh) is used to switch between terminals. the remaining 7 bits can be used to set the bit rate. bit 7 0= terminal 1, 1= terminal 2 bit 6 to 0 bit rate=f system /(4 * n) where n is the value of bits 0 to 6 and the setting value (0 = reset state means n = 128). a complete telegram is assembled by the software out of individual sections. each section contains an 8-bit data. this data is written into one of the nine possible control-data registers. de- pending on the chosen address, a certain part of an i 2 c or im-bus cycle is generated. by means of correspond- ing calling sequences it is therefore possible to join even very long telegrams (e.g. long data files for auto incre- ment addressing of i 2 c slaves). the software interface contains a 3 word deep fifo for the control-data registers as well as for the received data. thus all im and most of the i 2 c telegrams can be transmitted to the hardware without the software having to wait for empty space in the fifo. all address and data fields appearing on the bus are constantly read and written into the read-fifo. the software can then check these data in comparison with the scheduled data. if a read instruction is handled, the interface must set the data word ffh so that the re- sponding slave can insert its data. in this case the read- fifo contains the read-in data. if telegrams longer than 3 bytes (1 address, 2 data by- tes) are received, the software must check the filling condition of the control data fifo and, if necessary, fill it up (or read out the read-fifo). a variety of status flags is available for this purpose. moreover, in the i 2 c mode the ack-bit is recorded sepa- rately on the bus lines for the address and the data fields. however, the interface itself can set the address ack=0. in any case the two ack flags show the actual bus condi- tion. these flags remain until the next i 2 c start condition is generated. to minimize disturbances generated by the i 2 c signals, the fall times of both the i 2 c-scl and i 2 c-sda outputs on both i 2 c terminals are increased to one f system cycle while its output currents are decreased to one third of its maximum. thus by switching from high to low, it takes one f system cycle until the maximum driver cur- rent is switched on. it depends on the sizes of the (exter- nal) load capacitance and pull-up resistor when the low level is reached (see fig. 28 ). this feature is only ac- tive when the port output buffers are current-controlled, i.e., bit 5 of the ahardware control registero, address 209h, is set to `1'. capacities on any of the i 2 c pins should not exceed 100 pf. bigger capacitors could effect higher disturbances. r load should be equal to or greater than 2 k w. ccz 3005k preliminary data sheet 12 micronas fig. 27: i 2 c/im-bus interface address decoder wr_data (chosen address = control info) sr in out transmit fifo 3 x 11 wr d 0 to d 7 control receive fifo 3 x 8 d 0 to d 7 receive logic half full sr q sr q ready transmit logic empty start condition resets ack flags 3 2 terminal 1 p12 to p1 4 terminal 2 d 0 to d 7 rd_status (2d7h) dat or adr ack p10, p11 dat_ack adr_ack ccz 3005k preliminary data sheet 13 micronas fig. 28: principle of i 2 c signal outputs current reduction, during first t osc , after switching from high to low 1r t1 t2 2r r load c load 100 pf v sup 2 k w f osc /2 i 2 c qq fig. 29: current reduction active, bit 5 of `hardware control register' set to `1' r load = 2 k w, c load = 100 pf, recommended i 2 c clk f 2 out fig. 210: current reduction active, bit 5 of `hardware control register' set to `1', r load = 1 k w, c load = 100 pf, not recommended i 2 c clk f 2 out fig. 211: current reduction inactive, bit 5 of `hardware control register' set to `0', r load = 2 k w, c load = 100 pf i 2 c clk f 2 out fig. 212: current reduction active, bit 5 of `hardware control register' set to `1' , r load = 2 k w, c load = 350 pf, not recommended i 2 c clk f 2 out ccz 3005k preliminary data sheet 14 micronas table 24: i 2 c and im-bus interface registers address function 2d0h(w) generates i 2 c start condition, () g transfers data as i 2 c address and sets address ack=1 2d1h(w) same as above, ack=0 2d2h(w) output 8 i 2 c data bits, set ack=1 2d3h(w) same as above, set ack=0 2d4h(w) output 8 i 2 c data bits, () sets ack=1, generates i 2 c stop condition 2d5h(w) same as above sets ack=0 2d6h(r) receives fifo 2d7h(r) status flags: bit 0 not used bit 1 1= receive fifo empty bit 2 1= contr-data- fifo half full bit 3 1= bus busy bit 4 i 2 c data ack bit 5 i 2 c adr ack bit 6 aoroed ack bit 7 not used 2d8h(w) generates im-address field 2d9h(w) generates 8 im-data bits 2dah(w) generates 8 im-data bits and the im-stop condition 2dbh(w) terminal select & speed for example, the software has to work off the following sequence (ack = 1) to read a 16-bit word from an i 2 c device address 10h (on condition that the bus is not ac- tive): write 21h to 2d0h write 0ffh to 2d2h write 0ffh to 2d4h read dev. address2d6h read 1st databyte 2d6h read 2nd databyte 2d6h the value 21h in the first step results from the device ad- dress in the 7 msbs and the r/w-bit (read=1) in the lsb. if the telegrams are longer, the software has to ensure that neither the control-data-fifo nor the read-fifo can overflow. to write data to this device: write 20h to 2d0h write 1st data byte to 2d2h write 2nd data byte to 2d4h the bus activity starts immediately after the first write to the control-data-fifo. in the i 2 c mode the transmis- sion can be synchronized by an artificial extension of the low phase of the clock line. transmission is not contin- ued until the state of the clock line is high once again. thus a slave (software slave!) can adjust the transmis- sion rate to its own abilities. the i 2 c/ im-bus interface is a pure master system, multi- master busses are not realizable. the clock and data terminal pins have open-drain out- puts. the im-bus-ident line (terminal 1 only) is a push- pull output stage (see chapter 3.6.5. on page 54). check receive fifo empty flag (bit 1, 2d7h) be- fore read ccz 3005k preliminary data sheet 15 micronas 1 2 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 2 1 4 fig. 213: start condition i 2 c-bus fig. 214: single bit on i 2 c-bus fig. 215: stop condition i 2 c-bus fig. 216: im-bus start condition fig. 217: single bit on im-bus fig. 218: stop condition im-bus 1 1 4 sd scl 1 sd scl repeated 7 times sd scl 3 4 ident data clock 1 4 1 4 1 4 data clock ident ident 1 on the 8th address bit only clock stays high on the last data bit before stop 1 2 data clock ident 1 2 unit = bit-period ccz 3005k preliminary data sheet 16 micronas 2.12. a/d converter the analog voltages at 5 pins of the ccz can be con- verted to an 8-bit digital value. with an input multiplexer one of these five inputs is selected. the input voltage is `sampled and held' during conversion time. conversion gets started with writing the number of the desired ana- log input pin into the `analog input select and status' register (address 2a8h). after waiting until the `end of conversion' (`eoc') flag in this register (bit 7) is set to `1', the result is available in the `a/d converter output' value register (address 2a9h). the byte representing the analog voltage at the chosen adc input pin is evaluated by digital value = integer value of (256 x v ia /v supa ) . v ia = analog input voltage v supa = analog supply voltage the result of this equation is valid for gnd a < v ia < v supa. for v ia v supa the digital value is its maximum: ffh. the converter needs 68 oscillator clock cycles to sample an input, so with a 12 mhz crystal it takes 5.67 m s to con- vert an analog value. during this time the input voltage should be kept as stable as possible (see fig. 219). the `eoc' flag is comparable with a busy signal and only readable. it is reset (set to `0') by writing into the `analog input select' register and choosing one of the 5 analog inputs that starts conversion. a ccz reset also resets the `eoc' flag and selects the adc0 input pin. analog input select and status register (address 2a8h): bit 7: eoc-flag (read only) bits 2 to 0: number of analog input pin (0 to 4) (write only) important: the adc hardware must be enabled before the first con- version after reset can be started, by setting bit 3 of the `hardware control' register (addr. 209h) to `1'. then it is necessary to wait for 68 oscillator clock cycles before the first conversion can be started, by writing the desired adc input number into the `analog input select' register. any conversion started earlier delivers useless results. application tips: the input capacitance of an analog input is about 23 pf. the maximum input current depends on the voltage step at the input capacitance and has to be considered when calculating the signal voltage divider. an external capa- city between the adc pin and gnd should have a value of at least 10 nf. v ia should be as stable as possible dur- ing sample time. v supa must not exceed v sup ! fig. 219: a/d converter input ccz t sample = t on = 68 t osc v ia 23 pf fig. 220: a/d converter diagram 123 00 01 02 fd fe ff digital value v ia [lsb] 253 254 255 ccz 3005k preliminary data sheet 17 micronas 2.13. closed caption acquisition 2.13.1. video input the ac-coupled composite video input signal is applied to the video in pin where the negative horizontal sync tip is clamped to a value of 1.911v dc via a1. the gated sync tip clamp circuit is designed to work with a 0.1 m f coupling capacitor. the run-in clock of the closed cap- tion signal is averaged by r1 and c1. c1 is an external capacitor with a value of 560 pf. the resulting average level is taken as the optimum level for slicing the digital data which follows the run-in clock. it is important for c1 to hold the slicing level for a whole frame (33.2 ms). the best slice level, in terms of common mode range for the chip, is one half of the minimum supply voltage for the ccz: 4.75v : 2= 2.375v. since a 1 vpp video input signal is nominal the clamp level should set the 25 ire point (data slice level) for the 1 vpp case to 2.375v. this is done by clamping the sync tips to 1.911 v (2.375 v0.464 v). table 25: video input levels, clamped, in volts video signal input level [ire] clamp level at video signal input 1.0 v pp [v] clamp level at video signal input 2.0 v pp [v] remarks 100 2.911 3.911 (white) 50 2.554 3.196 25 2.375 2.839 (slice) 7.5 2.250 2.589 (black) 0 2.196 2.482 (back porch) 40 1.911 1.911 (sync) the data slicer consists of an on-chip low-pass filter and a high-speed comparator. the sliced data passes through a glitch filter which ignores spikes of less than three f xtal (12 mhz) periods in duration. the data is then conditioned in a preprocessor stage and trans- ferred to the cpu. the software reads the data from the selected caption line(s) and decodes the caption data further. fig. 221: line 21 field 1 data signal format two 7-bit + parity ascii characters (data) start-bit blanking level 7 cycles of 503 khz (clock run-in) color burst +40 +20 0 20 -40 ire units 33.764 m s 0.53h 3.972 m s (0.06h) 12.91 m s (0.20h) 25 27.452 m s (0.43h) 10.074 m s (0.16h) 51.268 m s 61.342 m s 0.965h +60 ccz 3005k preliminary data sheet 18 micronas fig. 222: principle of video input for the detection of closed caption data (1.911 v) detect video (port 237h) v clamp +142 mv f xtal = 12 mhz z 1 z 1 sync tip clamp gate 8-bit sr 8-bit latch 8-bit input port data bus f xtal /32 3 sample averager peak or gated sync-tip clamp composite video in (1 v pp to 2 v pp ) s licer cap (external) a1 a2 clock run-in key glitch filter v clamp s1 s2 c1 c2 r1 r2 10k 560 pf f xtal f xtal f xtal f xtal f xtal/4 note: if sync_detect = 1 then s1 always open 2.13.2. closed caption data detection the sliced data are shifted serially into an 8-bit register with the f xtal /4 as clock signal. the f xtal /32 latches these 8 bits so that, as byte, they are available for the processor at register 23fh. as every f xtal /32 period overwrites the previous latched data, the cpu has to read this register fast enough to get all data. the soft- ware part doing so could look like this: ;capture data port address: capture_data_ equ $23f ; variables: capt_buffer_ equ $50 ; 26 bytes caption data buffer no_of_data_ equ capt_buffer_+26 ; data counter capture ldx #0 ; init pointer to captured data in ram lda #26 ; acquire 26 samples sta no_of_data_ capture_ loop lda capture_data_ ; read sliced data ; 4 cycles sta capt_buffer_,x ; store it in ram ; 4 cycles inx ; point to next location in ram ; 2 cycles cpx no_of_data_ ; done 26 samples yet? ; 3 cycles bne capture_loop ; no, so keep looping ; 3 cycles ; ; 16 cycles ccz 3005k preliminary data sheet 19 micronas it is important to have all variables used here defined in the address space of the zero page, and not to cross a page boundary with the loop, as otherwise the execution time increases. with 16 processor cycles the sliced data scan rate of this sequence is 12 mhz/2/16 = 375 khz at a crystal frequency of 12 mhz. this is exactly the clock of the 8-bit slice data latch of f xtal /32. caption data are now in the ccz memory and have to be decoded. the caption data rate is 503 khz. the shift rate of the slice data register is f xtal /4 = 12 mhz/4 = 3 mhz. this is al- most 6 times the caption data rate of 6*503 khz = 3.018 mhz. thus, in the received bit stream, a bit of the caption data is represented by 6 successive sample bits of the same value (the levels of the clock run-ins represented by 3 bits). as the caption data rate is higher than the scan rate and the phases of both clocks are not synchronized, it may occur that a caption data bit is detected as 5 sam- ple bits only: clock-drift = (503 khz- 500 khz)/500 khz = 0.6%. the software to decode the captured data has to consid- er this item. the decoding of the data can be done by several methods: either by comparing the bit-pattern for the last clock run-ins, the start condition and the data bits, or by searching the start condition first, the last clock run-ins next, and then the data, by checking one or several adjacent bits in the center of the six bit por- tions. the following example shows what the bit pattern of captured data in the ccz memory could look like: captured data in memory: capt_buffer_: fcb 00h, 00h, feh, e7h, 3dh, 8fh, e3h, 00h fcb f0h, ffh, c0h, 0fh, 00h, c0h, 0fh, fch fcb 00h, 00h, 00h, c0h, ffh, 03h, 00h, 00h fcb 00h, 00h these data are gathered from the following bit stream (as the reception starts with the least significant bits, the notation starts with them, from left to right) : 00000000 00000000 01111111 11100111 10111100 11110001 11000111 00000000 00001111 11111111 00000011 11110000 00000000 00000011 11110000 00111111 00000000 00000000 00000000 00000011 11111111 11000000 00000000 00000000 00000000 00000000 the start-bits begin in the eighth byte: 00000000 00000000 01111111 11100111 10111100 11110001 11000111 00000000 ccz 3005k preliminary data sheet 20 micronas fig. 223: gate and window logic nmi 65c02 sync_detect (port 237h) slicer_out f xtal/4 f xtal/32 f xtal/4 dq dq dq 3-line mode nmi supp. wr_236h 1 ccz 3005k preliminary data sheet 21 micronas 2.13.3. gate and window logic the gate & window logic is responsible for keeping track of which video field is present at any given time (odd or even field, also known as afield 1o or afield 2 o ), which video line is present (1 to 262 for ntsc, 1 to 312 for pal/secam) and where we are within the line. by keeping track of these three values the gate & window logic is able to produce the run-in-key pulse, which is used by the front-end hardware to determine the best slicing level and to inform the cpu when it is time to start acquiring data from the closed caption video line. the gate & window logic requires a horizontal sync input in addition to the vertical sync input. the active horizontal and vertical pulse width must be at least 6 t osc, i.e., with a crystal frequency of 6 mhz, it must be greater than or equal to 1 m s. vertical timing every tv video frame is made up of two video fields, an odd field and an even field. the ccz 3005k must be able to distinguish an odd field from an even field because the telecaption data can appear on either or both fields. the ccz is able to distinguish between odd and even fields, taking advantage of the fact that there is a half-line offset between fields (since 525 & 625 are odd numbers). the difference is measured and used as a basis for determin- ing which field is which. note that the position of the vert sync and hor sync is also a function of the sync proces- sor circuit used to provide vert and hor sync. the phas- ing of vert sync can change from one type of sync pro- cessor to another; but there will always be a measurable difference between the fields. therefore it is up to the user of the ccz to determine what phasing is suitable for his particular sync processor. the gate & window logic measures the difference in phasing between vert sync and hor sync with an 8-bit asampleo counter (`vertical sync phase value' register, addr. 23dh). this counter is clocked at f xtal /4 (3 mhz) and is cleared by the hsync signal, either derived from the hsync pin or the composite video, determined with bit 1 in the `window logic control register2', (addr. 237h). the active edge of vertsync latches the contents of the counter and generates an interrupt request (nmi). the cpu reads the contents of the latched sample counter and determines whether the new field is odd or even. the logic keeps track of lines with a 9-bit line counter which is clocked each horizontal line and cleared by vert sync. the desired closed caption line is provided from a loadable register to a comparator as 8 bits. the 9th bit is hardwired alowo, so the closed caption line must be in the first 256 lines of the field. the closed captioning decode is combined with the afield selecto line to generate an interrupt to the cpu. the field line select is provided by the cpu since it knows what field it is trying to find data on. the closed captioning decode also enables the run-in key. the acquisition clock is enabled by the cpu at the be- ginning of the acquisition interrupt routine. the program keeps the acquisition clock enabled for a few cycles be- yond the closed caption line to ensure that all of the data has been read from the shift register in the front end. the acquisition clock, f xtal /32, is combined with the closed caption line decode. the cpuso input is active after reset. the cpu needs to know what causes the interrupt (nmi) since the vertsync pulse also generates an nmi. this is accomplished by feeding the vert sync pulse directly into a status register. if this bit is high during the interrupt then the cpu assumes this is a vert sync interrupt. this leads to the constraint that the vert sync signal must re- main high for at least one horizontal line period and must be low during the closed caption line. this is normally the case for sync processors anyway. also, the vert sync in- terrupt routine must be completed before the acquisition interrupt occurs (see fig. 225). fig. 224: vertical timing nmi run-in key closed caption line & field select field select closed caption line line counter vert sync composite video field n1 field n field n+1 (emu pin 18) (emu pin 27) (emu pin 25) ccz 3005k preliminary data sheet 22 micronas video line no. composite video nmi hsync vsync closed caption line counter video line no. composite video nmi hsync vsync closed caption line counter fig. 225: closed caption line detection fig. 226: video detection closed caption line detection: `video detect'-bit (= bit 1 of window logic control register 2, addr. 237h) = `0' the closed caption line number is defined in the nmi interrupt function. the line counter is triggered by the hsync signal. video detection: `video detect'-bit (= bit 1 of window logic control register 2, addr. 237h) = `1' the closed caption line number is defined in the nmi interrupt function. the line counter is triggered by the hsync-clamped composite video signal. ccz 3005k preliminary data sheet 23 micronas horizontal timing the horizontal timing is based on the hsync input derived from the hsync 1 -pin (default) or the hsync 2 pin (p27 in special mode), defined with bit 3 in the `window logic control' register (addr. 237h). the critical hori- zontal rate job performed by the ccz's gate & window logic is to generate the run-in key pulse during the tele- caption line. the run-in key signal may be measured on pin 27 of the emulator chip. its start time is program- mable in register 23bh, while its stop time is determined in register 23ch. an optimized timing of the run-in key referred to the composite video signal delivering the caption data on pin 122 of the ccz 3005k emulator chip is given in figure 228. the key pulse is used by the front-end circuit to establish the optimum data slicing level. the key pulse start and stop points along the horizontal line are decoded from the sample counter. the decodes are programmable. the start/stop points are combined with the aclosed caption lineo signal to form a run-in key that occurs only during the closed caption line. fig. 227: horizontal timing composite video (emu pin 122) sample counter start end run-in key (emu pin 27) nmi (emu pin 18) closed caption line & field select (emu pin 25) acquisition clock sync-tip clamp gate (emu pin 26) closed caption line start of field 1 start of field 2 composite video h sync vert sync sample counter nmi (emu pin 18) composite video h sync vert sync sample counter nmi (emu pin 18) ccz 3005k preliminary data sheet 24 micronas composite video (emu pin 122) run-in key (emu pin 27) sync-tip clamp gate (emu pin 26) fig. 228: optimized run-in key and sync-tip clamp a sync tip clamp gate is also decoded from the sample counter. this gate will start a few counts after the leading edge of hsync and will end a few counts before the trail- ing edge of the hsync portion of the video signal. the start and stop counts are programmable. the sync tip clamp gate signal may be measured on pin 26 of the emulator chip. its start time is programmable in register 239h, while its stop time is determined in register 23ah. an optimized timing of the sync tip clamp gate referred to the composite video signal delivering the caption data on pin 122 is given in figure 228. the sync tip clamp gate is used by the front-end circuit to clamp the incom- ing video to a known reference level. 3-line mode the use of certain video sources (for example vcrs) may cause problems in finding the caption lines (time base jitter). however, owing to the 3-line-mode the wandering of the caption line can be noticed without loosing data. in the 3-line mode 3 consecutive lines are sampled and saved in a ram-buffer via software. nor- mally the data line lies in the middle, that is, the second recorded line. in this line only the run-in key control sig- nal is generated. if the software cannot detect any cap- tion data there, the line before and the line after are searched for data. if data is to be found there, it is de- coded as usual. also, the software corrects the caption counter ((23eh) so that the caption line lies in the middle of the three lines again. thus the caption decoder can follow the deviations of the caption line. naturally this method uses up more ram space and, in that case, more computing power. video-detect mode (see fig. 226) for fade and mute it is necessary for the software to rec- ognize the presence of a video signal. the hardware of the caption decoder can achieve this. the interrupt service routine for data capture can define a line by writing its number into the caption line register (23eh), and setting the window logic control unit to avid- eo detect modeo by programming bit 1 = `1' of the window logic control register (237h). the processor will receive an interrupt (nmi) at the occurrence of the specified line. the time delayed up to this interrupt is given by evaluat- ing the system counter word in registers 203h and 204h. if no line interrupt occurs, the detection of the next v sync that is not derived from the video signal indicates the non-existing video signal. if the time up to the occur- rence of the line-interrupt is too short, this also means that no stable video signal is available. to detect the cor- rect sync-level on the video in pin a low-pass filter to ig- nore the color burst should be applied. the video detec- tion circuitry is designed for an input signal of 1 v pp . software interface address function 237h(w) window logic control bit 3 h sync select: `0' = h sync1 -pin `1 '= h sync2 -pin bit 2, `1'= gated clamp `0'= peak clamp bit 1, `1'= video det. mode (sync detect) bit 0, `1'= 3-line mode 238h(r/w) window logic control bit 7 level vsync pin (read only) bit 6 line counter nmi `0'= disabled `1'= enabled bit 5 `1'= cpu-so input enabled bit 4 `1'= half-dot rounding on bit 3 osd active (read only) bit 2 active edge of v sync : `0': rising, `1': falling bit 1 active edge of hsync for ac- quisition: `0': rising, `1': falling bit 0 active edge of hsync for osd: `1': rising, `0': falling 239h(r/w) sync tip clamp start bit 7 to 0 start pos. pos.= start pos.*4/ f xtal 23ah(r/w) sync tip clamp end bit 7...0 end pos. pos.= end pos.*4/ f xtal 23bh(r/w) run in key start bit 7 to 0 start pos. pos.= start pos.*4/ f xtal 23ch(r/w) run in key end bit 7 to 0 end pos. pos.= end pos.*4/ f xtal 23dh(r/w) vertic. sync phase (odd/even field detect) 23eh(r/w) caption line number nmi is disabled before this register is written for the first time 23fh(r) captured data ccz 3005k preliminary data sheet 25 micronas 2.14. osd a powerful on-screen display (osd) is provided on the ccz 3005k. many novel approaches were made to save chip area. the most important area saving tech- nique was to eliminate the redundant storage of dis- played data. traditional display devices transfer fixed text data (such as prompts, menus, graphics etc.) from program rom to the display ram. the ccz's osd, however, is able to display text directly from program rom. additionally, the character font table may be lo- cated in the program rom. this offers the ability to size the table exactly as required. furthermore, specific characters and symbols can be defined. a second char- acter font may be defined in unused portions of ram which would allow you to create characters aon-the-flyo. the ability of the osd hardware to access font and dis- play data directly from program rom was facilitated by incorporating direct memory access (dma) hardware on chip. a minor slow-down of the processor occurs when the dma hardware is active. the slow-down of the pro- cessor is related to how many characters are on screen and how many color changes occur from character to character. 2.14.1. summary of osd features 2 character sizes: 13 h x 8 w or 15 h x 8 w soft-scroll unlimited numbers of fonts, with any two active at a time attributes: flash, italics, transparent, underline 8 foreground and 8 background colors color palette (8 of 64 colors) line-locked display clock second color for one text line definable very effective for pull-down structures half-dot rounding 2.14.2. fonts two different fonts may be defined: one in rom and one in ram. the ram font can be changed by software. this makes it easy to provide foreign language charac- ter sets. the basic character set, which is common to all latin-based languages, for example, can be pro- grammed in the rom font, containing all characters in the range from ascii 32 to 127 i.e., the aprintableo ascii characters. the extensions of the character set that are specific to a language may be contained in the ram font. these characters can be accessed with off- sets to the rom font or by translating unique ascii char- acters with a table. 2.14.3. osd window start positions of the display are determined and changed (moved) by setting just two register values: y_start and x_start. there is no restriction on text and window size. pro- gram font 2 font1 font2 font 1 cpu osd memory text fig. 229: pointer model osd text h sync v sync r g b fast blank dis- play logic ccz 3005k preliminary data sheet 26 micronas 2.14.4. colors 2.14.4.1. osd attribute `color' `color' is a control byte that prefixes the data stream for the osd. it resides anywhere in the ccz memory, in rom or ram. example: fdb color ; define color fcc astringo ; display `string' the byte `color' defines the foreground and back- ground color of the characters that follow, until the next `color' attribute is encountered. osd attribute `color': bits 0 to 2: value 0 to 7 defining foreground color (color 0 to color 7) bits 3 to 5: value 0 to 7 defining background color (color 0 to color 7) bit 6: `0' or `1', if `1': color 0 is replaced by transparent bit 7: `1': marks color attribute. all other data (characters) have bit 7 = `0'. 2.14.4.1.1. attribute `transparent' if osd attribute `color' bit 6 = `1' and background col- or = `000' but the foreground color is different from `000', the (foreground) character(s) that follow are displayed on a transparent background, i.e., the video source sig- nal is visible instead of the background color. also the foreground color 0 becomes transparent with osd at- tribute `color' bit 6 = `1'. 2.14.4.2. available colors the ccz 3005k has 8 programmable colors. these col- ors are selectable out of a palette of 64 different values. each color consists of the 3 components red, green and blue. each of these components has 1 out of 4 different intensities. for example, the eight colors could be programmed to be compatible to those of the ccu 3005 c and ccu 3005 d. color 0 = black color 1 = blue color 2 = green color 3 = green/blue = cyan color 4 = red color 5 = red/blue = magenta color 6 = red/green = yellow color 7 = white table 26: color component intensity values intensity msb lsb off 0 0 1/3 0 1 2/3 1 0 maximum 1 1 with 4 different intensity values of 3 different colors, 4 ? 4 ? 4 = 64 different colors are possible. table 27: color palette register r (267h) g (268h) b (269h) address (color) reset value 0 0 0 0 red=green=blue=00 0 0 1 1 red=green=00; blue=11 0 1 0 2 red=00; green=11; blue=00 0 1 1 3 red=00; green=blue=11 1 0 0 4 red=11; green=blue=00 1 0 1 5 red=11; green=00; blue=11 1 1 0 6 red=green=11; blue=00 1 1 1 7 red=green=blue=11 ccz 3005k preliminary data sheet 27 micronas 2.14.4.3. color palette programming 6 register write accesses are necessary for the 3 palette registers to define the 8 possible colors. to program the 16 bits of each of these 3 registers, every register has to be accessed twice. the first write access programs the least significant 8 bits, and the second write access pro- grams the most significant 8 bits. each of the 8 program- mable colors is defined by three 2-bit intensity values: 2 bits for the red component, 2 bits for green and 2 bits for blue. all least significant bits of these 2 bit values form the first byte to be written (low byte), all msbs form the second byte (high byte). the bits at location 0 of the low and high byte correspond to color 0, bits at location 1 to color 1, bits at location 2 to color 2, ... and bits at location 7 to color 7. example: to get color 0 as light grey, choose 1/3 intensi- ty for each component: 1/3 red = 01 1/3 green = 01 1/3 blue = 01 it is not possible to program a single color on its own, thus all 8 selectable colors have to be programmed to- gether. the other 7 color values have to be defined be- fore (`x' is used instead of any `0' or `1' defining the other colors 1 to 7 in this example). the programming looks as follows: the value for 1/3 intensity red = `01'. the least significant bit of this value becomes bit 0 (for color 0) of color palette register red, low byte: lda #%xxxxxxx1 sta color_palette_register_red the most significant bit of intensity red becomes bit 0 (for color 0) of color palette register red, high byte: lda #%xxxxxxx0 sta color_palette_register_red intensity green = `01', least significant bit becomes bit 0, green, low byte: lda #%xxxxxxx1 sta color_palette_register_green the most significant bit becomes bit 0, green, high byte: lda #%xxxxxxx0 sta color_palette_register_green the same procedure applies to blue: lda #%xxxxxxx1 ;the `1' of `01' sta color_palette_register_blue lda #%xxxxxxx0 ;the `0' of `01' sta color_palette_register_blue a reset changes the color palette to the corresponding colors of the ccu 3005 c and ccu 3005 d (see palette register description in chapter `registers'). 2.14.4.4. color palette hardware a common resistor network is used for the generation of the different intensity levels. the output impedance is maximum 2 kohms. the following diagram shows the working principle. the color palette controls the 12 tran- sistors of the rgb intensity matrix. only one transistor per output is active at a time. fig. 230: color map, 3 x 2 bytes d 7 d 0 lsb lsb msb data bus ccz d 7 d 0 lsb msb msb data bus ccz d 7 d 0 lsb msb data bus ccz red (of color 7) color 0 red green blue ccz 3005k preliminary data sheet 28 micronas table 28: rgb output levels half-video level fb 1) rgb level at v sup = 4.75v at v sup = 5v at v sup = 5.25v `1' off 0 % 0v 0v 0v `0' off 0 % 0v 0v 0v `0' on 0 % 0v 0v 0v `0' on 33 % 1,58v 1,66v 1,75v `0' on 66 % 3,16v 3,33v 3,5v `0' on 100 % 4,75v 5v 5,25v 1) the active level of the fast blank output is program- mable with bit 7 of the `osd separate color definition register' (addr. 266h). 2.14.5. fast blank output the `fast blank' output is active during any osd activi- ties, i.e.,: the display hardware controlled by the `fast blank' must only evaluate the ccz rgb outputs with `fast blank' = active. the polarity of the `fast blank' is programmable (`0' or `1' active). 2.14.6. half-video output the osd generates a `half-video' output signal to con- trol external hardware and subdue the video signal. this effects better readability of the osd, in particular if the video signal's color and contrast are similar to the osd signal's. the `half-video' is active instead of `color 1', no matter whether this color 1 is the background or fore- ground color. whatever the value of color 1 is defined to be (palette values), the `half-video' output becomes `1'-level and the rgb outputs become inactive (`0'-lev- el). the `half-video' output can be switched off (set to `0' throughout) by setting bit 0 of the `osd half-video con- trol' register to `1'. after reset, this bit is cleared (`0') and the half-video output is active. rgb 100% 66% 33% 0% 1 1 1 +5v fig. 231: principle of color palette t 100 t 100 t 100 t 66 t 66 t 66 t 33 t 33 t 33 t 0 t 0 t 0 ccz 3005k preliminary data sheet 29 micronas 2.14.7. using osd the osd is organized to display character streams (strings), i.e., data streams in the memory are inter- preted as osd attributes or display characters. via font data the display characters are converted into display pixels. a number of registers offer a convenient method of telling the osd `where' and `what' shall be displayed. as only 8 bits can be handled at a time, parameters with more than 8 bits in size require multiple writes to the same register, with the msbyte written first. the (un- used) high bits of such registers should be set to `1'. 1) so, for example, to program 12ch as `last active scan line', an affho would first be written into address 261h and then a a2cho. to avoid a flickering display, writing to the osd register should occur synchronized with the vertical synchro- nization signal. the active horizontal and vertical pulse width must be at least 6 t osc, i.e., with a crystal frequency of 6 mhz, it must be greater than or equal to 1 m s. 1) disturbing effects caused by internal compare evalua- tions may appear if unused high bits of values with more than 8 bits are set to `0', and these values are pro- grammed without being synchronized to the horizontal synchronization signal. explanation of register functions: 238h(r/w) window logic control register 1: bit 7 level vsync pin (read only) bit 6 line counter nmi `0'= disabled `1'= enabled bit 5 `1'= cpuso input enabled bit 4 `1'= halfdot rounding *) on bit 3 osd active **) (read only) bit 2 active edge of vsync: `0': rising, `1': falling bit 1 active edge of hsync for ac- quisition: `0': rising, `1': falling bit 0 active edge of hsync for osd: `1': rising, `0': falling *) halfdot rounding is not defined for horizontal start position (reg. 0262h) less than 6 and greater than 46. **) the osd active bit is set to `0' at the beginning of the `first active scan line'. it is set to `1' either after the ac- cess to the last scan line of the active display part, de- fined in `last active scan line', or after the access to the text-end character. 260h(w) `osd first active scan line' 9 bits: specifies the start scan line of the osd window. 261h(w) `osd last active scan line' 9 bits: determines the last scan line of the osd window to be displayed. note that it is possible to set this value to a number that causes the last character lines to be acut offo. this is a desirable feature when smooth scrolling is in operation. 262h(w) `osd horizontal start position' 6 bits: determines horizontal start position of the osd window in character steps. (must be greater than 1!) . don't use values less than 6 or greater than 46 if `halfdot rounding' is enabled (`halfdot rounding' is enabled if bit 4 in register 0238h = `window logic control register 1' is set to `1'). the size of one horizontal character step is 8 pixels. (fine adjust in pixels is possible with `osd horizontal start fine adjust', address 26fh). remark: the horizontal stop position of the osd window is determined in the osd data stream with the attribute `cr' (= 0dh) or `end' (= 0ch). 263h(w) `osd control register', 8 bits: bit 7 `1' = caption mode `0' = osd mode must be set to `1' for caption data. bit 6 `1' = display active bit 5 `1' = flash off `0' = flash on all characters between the attributes `flash on' and `flash off' are displayed only if this bit is set to `0' bit 4 `1' = 13x8 font `0' = 15x8 font bit 3..0 first active character scan line: determines the start scan line of the first character row of the osd window. this ability allows the smooth scrolling feature to look correct at the top of the window. ccz 3005k preliminary data sheet 30 micronas 264h(w) `osd text start address register', 16 bits: points to the first character of an osd data stream. all subsequent characters are encountered until either the osd attribute `end' or the `vertical stop position' determined in the specific register (address 261h) limits the osd window. remark: the horizontal expansion of the osd window is determined in character rows which are terminated with `cr' (=0dh). 265h(w) `osd separate colored line', 9 bits: start scan line value for a single character line to be displayed with a separate color. color attributes as part of the osd data stream (display string) have no effects on the one character high scan lines selected by this register. the color is defined in the `separate color definition register'. thus an entire character line may be high- lighted by simply writing its start scan line into this register. this highlighted character line may overlap the boundary of two neighbored ordinary character lines. thus it can be soft-scrolled through the osd window. 266h(w) `osd separate color definition register' and two more control bits, 8 bits: bit 7: fast blank output level: `1'= active high `0'= active low bit 6: `1'= replace black by transparent `0'= don't replace black by transparent separate color definition: bits 5 to 3: background color (color no. 0 to 7) bits 2 to 0: foreground color (color no. 0 to 7) 26ah(w) `osd half-video control register': bit 0: `0'= disable half-video (default after reset), half-video output pin level=`0' `1'=enable half-video 26eh(w) `osd font 1, font 2, start addresses', 32 bits: write in the order msb font1 (first access) lsb font 1 msb font 2 lsb font 2 (last access) two pointers to the start of character fonts. font 1 displays all characters in the range of 0 to 15h, and font 2 displays all characters in the range between 20h to 7fh. the osd assumes the address of the first character (= 00h) as font pointer. 26fh(w) `osd horizontal start fine adjust and display modes': bit 7 `1'= horizontal shadow active bit 6 `1'= blank display bits 5..3 not used, set to `0' bits 2..0 horizontal start fine adjust ccz 3005k preliminary data sheet 31 micronas 2.14.8. osd attributes the osd receives control information from attribute by- tes which are part of the osd data stream. they reside in the ccz memory (ram or rom) together with the text characters to be displayed. 80h to ffh: `color' bit 7 `1'= color code (to distinguish this attribute from ascii or control codes). bit 6 `1'= color 0 replaced by transparent bit 5,4,3= background color (color no. 0 to 7) bit 2,1,0= foreground color (color no. 0 to 7) 01h: `underline_on' all subsequent characters are underlined until the osd attribute `underline_off' or `end' is encountered 02h: `underline_off' see `underline_on'. 03h: `flash_on' the following characters up to the attribute `flash_off' or `end' are displayed only if the `flash' bit in the `osd control register' is set to `0' (= bit 5, addr. 263h). the flashing occurs only when the flash bit is toggled. this could be done in the interrupt timer function, for example. 04h: `flash_off' see `flash on'. 05h: `italics_on' all subsequent characters are displayed in italics format until the osd attribute `italics_off' or `end'is encountered. 06h: `italics_off' see `italics_on'. 07h: `transparent' for this character space the underlying video image is shown. 08h: (in standard osd mode only) `double_underline_on' like `underline_on' (01h) but the last two character scan lines are used instead of only the last one. `underline_off' (02h) or `end' turns this mode off again. 09h: (in standard osd mode only) `font_1 and_2 ' automatic change of font_pointers depending on ascii-value (default mode, initialized by reset and the active v sync edge) 0ah: (in standard osd mode only) `font_1_only' osd uses only font_1 0bh: (in standard osd mode only) `font_2_only' osd uses only font_2 0ch: `end' end of the osd. your text must end with this code. 0dh: `cr' carriage return. the following characters are displayed in the next text line. the osd insertion must be terminated with cr (0dh) or end (0ch) before the next hsync! ccz 3005k preliminary data sheet 32 micronas 2.14.9. font definition the osd has no separate character generator, but the definitions of the characters reside in rom and/or ram of the ccz. each character is defined by 16 bytes. one byte corresponds to the pixels in the scan line on the screen, the msb being the first (leftmost) output. the fol- lowing 15 addresses contain the pixel information for the remaining scan lines of the character. three bytes for the 13x8 characters and one byte for the 15x8 charac- ters are left unused. for example, the definition of the letter aao in the 13x8 matrix could look as follows: bit 7 6 5 4 3 2 1 0 n =00h n+1 x =10h n+2 x x =28h n+3 x x =28h n+4 x x =44h n+5 x x =44h n+6 x x =82h n+7 x x x x x x x =feh n+8 x x =82h n+9 x x =82h n+10 x x =82h n+11 =00h n+12 =00h n+13 0 0 0 0 0 0 0 0 =00h n+14 0 0 0 0 0 0 0 0 =00h n+15 0 0 0 0 0 0 0 0 =00h osd insertion must be terminated with `cr' (0dh) or `end' (0ch) before the next hsync! the addressing of the pixel pattern to be displayed is giv- en by: address= font pointer+ascii*16+scan line with scan line= 0...12 if the font table does not start with the ascii character 00h, the font pointer has to be programmed with the cor- responding offset. if, for example, the font table starts with the letter aao (ascii 65) at address ano, the the fol- lowing value results for the font pointer: font pointer = n(65*16) this assumes, of course, that the ascii representation is used. font pointer 1 is used to access ascii charac- ters 00h..1fh, font pointer 2 is used to access ascii characters 20h ... 7fh. a single continuous font table re- sults when font pointer 1 and font pointer 2 are set to the same address. 2.14.10. soft-scroll to produce soft-scroll, the software regularly changes the start-scan line of the display (263h, bits 3 to 0). the display of the text line designated by the text pointer starts with this scan line. when the value reaches the last scan line, the text pointer is set to the beginning of the next text line and to the start scan line. thus the text slowly seems to move upwards. the lower edge is de- fined by the parameter y_end. the scroll speed and the direction are determined by how fast the software incre- ments (or decrements) the start scan line register. to avoid flickering, the change should be effected during the vsync interrupt routine. ccz 3005k preliminary data sheet 33 micronas 2.15. cursor a cursor can be displayed independently from the osd output . this cursor is always displayed at the top. it can be of any shape within a field of 24 24 pixels. the logic needs a pointer to a cursor definition bit map. this bit map must be defined somewhere in the cpu address space. the other control registers define the three se- lected colors, the position of the upper left corner, the fast blank polarity and the half-video or transparent mode. there can be multiple cursor bit maps in memory. changing the cursor shape just needs a new cursor pointer content. 2.15.1. cursor definition two masks of 24 24 pixels define the shape. this gives 2 bits per pixel for color definition. if both mask-bits of a cursor pixel are zero, the background (osd or video) is displayed instead of a cursor pixel. every other mask-bit combination (01b, 10b and 11b) has a 3-bit color defini- tion register (col_m1 to col_m3). the content of the se- lected register will be used as address for the color pal- ette: mask 1 pixel mask 2 pixel dis- played color spec. mode 0 0 back- ground 1 0 col_m1 trans- parent (video) 0 1 col_m2 1/2 video 1 1 col_m3 cursor bit map bit 7 bit 0 left pixel right pixel right pixel left pixel mask 1, line 2 mask 2, line 2 mask 2, line 1 mask 1, line 1 x y 24 24 pixel count vsync hsync x-position (9 bits) col_m1 col_m2 on/off 273h y-position (9 bits) col_m3 transp. 275h 271h 272h 274h 270h x fb-pol hvideo lsb lsb lsb lsb lsb lsb cursor pointer etc.. fig. 232: register model cursor ccz 3005k preliminary data sheet 34 micronas the cursor logic reads the bitmap using dma cycles. there is a 16-bit pointer to a block of 3*2*24 = 144 bytes. for every cursor scanline the logic needs 6 bytes: 3 by- tes(= 24 pixels) for mask1, and 3 bytes for mask2. this explains the cursor definition format: cursor pointer line1, mask1, byte1 address n line1, mask1, byte2 n+1 line1, mask1, byte3 n+2 line1, mask2, byte1 n+3 line1, mask2, byte2 n+4 line1, mask2, byte3 n+5 line2, mask1, byte1 n+6 line2, mask1, byte2 n+7 line2, mask1, byte3 n+8 line2, mask2, byte1 n+9 line2, mask2, byte2 n+10 line2, mask2, byte3 n+11 etc.. even if the osd has the character rounding active, the cursor logic displays the same 24*24 pixels on both fields. the visible cursor field is therefore (on interlaced displays) 24 pixels*48 scan lines wide. 2.15.2. cursor position the cursor can be positioned with pixel resolution. two 9-bit registers define the x and y position of the upper left corner of the cursor field. the logic uses the same display clock, h-sync and v-sync signals as the osd. this guarantees a perfect match between osd and cur- sor positions. the osd has a character-based x and a scanline-based y position scheme, the cursor needs positions in pixel resolution. note: the x-fine register in the osd acts as an offset of the osd_hsync. changing this register will move both, the osd and the cursor. it is not necessary to include the x-fine position into the cur- sor position calculation. 2.15.3. moving and changing the cursor the cursor logic has 6 i/o registers. changing only the cursor position requires 2 to 4 write operations, chang- ing the shape and the position needs 6 writes. the con- tent of the registers from the first write to the last write is intermediate and can therefore produce jumping effects, wrong colors or wrong cursor shapes. to avoid these ef- fects, disable the cursor with the first write and synchro- nize your cursor control software with vsync_osd. en- able the cursor again as last write to the corresponding control register. doing all the changes after vsync gives enough time to complete the modifications before the first cursor scanline is reached. 2.15.4. cursor control bits the color `col_m1' can be replaced by transparent, the color `col_m2' by 1/2 video, if the corresponding control- bit is set. instead of the cursor pixel the video pixel will be displayed (with reduced intensity for `1/2 video'), even if the cursor is over an osd area. this is different from the `background' color (both mask bits=0): `background' dis- plays the background of the cursor (osd or video), `transparent' always uses the video as color. the fb_polarity bit selects the active state of the fb sig- nal during the display of the cursor field. this flag must be set to the same level as the fb_select bit in the osd. the on/off flag allows the software to enable or disable the cursor. ccz 3005k preliminary data sheet 35 micronas 2.15.5. cursor dma the cursor and the osd access the cpu memory via dma. the dma of the cursor logic is done right after the osd-h-sync of a cursor-scanline (this is a scanline that shows cursor pixels, 24 lines per field). six subsequent dma cycles transfer the two mask patterns for one cur- sor scanline into the display buffer of the cursor logic. collisions with the osd-dma are avoided since it is not allowed to select osd positions less than 1 (without rounding) or 6 (with rounding): the dma cycles are com- pleted before the osd can become active. (note: osd- x-positions count in character steps, an x-position in- crement of one is equivalent to 8 bus cycles). system clock hsync_osd cursor dma system bus cursor_load cursor_pointer cpu cursor cursor cursor cursor cursor cursor cursor cpu cpu cpu cpu cp cp+1 cp+2 cp+3 cp+4 cp+5 cp+6 fig. 233: cursor dma timing active edge select osd cursor transparent & 1/2 video logic d 0 to d 7 d 0 to d 7 d 0 to d 7 color palette fb to nmi control r g b fb 1/2 video hsync_osd vsync_osd selected vsync_osd cursor_color display_cursor fb_cursor, hvideo_cursor osd_ color sync mux d 0 to d 7 v int h int fig. 234: osd and cursor block diagram ccz 3005k preliminary data sheet 36 micronas 2.16. h & v sync generator the osd and cursor logic of ccz 3005k needs horizon- tal and vertical synchronization inputs to generate the in- ternal timing signals. if these sync inputs are not stable (e.g. during channel search) the osd will not have a stable position on the tv screen. the h & v sync generator delivers stable horizontal and vertical sync pulses which can be used to synchronize the osd. via a programmable sync multiplexer the osd can be connected either to the h sync and v sync input pins or the output signals of the h & v sync generator (see fig. 235). the switching of the sync multiplex- er should only occur when the osd is inactive! after reset the osd is connected to the h sync and v sync in- put pins. the h & v sync generator can be used either in free run- ning or in tracking mode. in free running mode the h & v sync generator simply counts with f system and gener- ates syncs at fixed positions (h = 384, v = 312/262). in tracking mode the sync generator tries to follow the h sync and v sync input signals, but only within pro- grammable limits. both horizontal and vertical tracking can be programmed independently. if tracking is en- abled, a 5bit speed value can be set which defines how fast the internal counters will be adapted (for example: h = 384 10, v = 312 5). r g b fb osd & cursor h & v sync generator v osd h osd v sync h sync '1' '0' sync mode '1' '0' sync mux active edge select sync format fig. 235: osd synchronization ccz 3005k preliminary data sheet 37 micronas the output signals of the h & v sync generator can be programmed in various ways to adapt to different ap- plications. both outputs can be inverted independently and can be combined into a composite sync signal. the vertical field length can be set to pal or ntsc mode. h 22 311 261 v 123 23 310 260 309 259 24 h osd =v & h v osd =v ^ h mux mux inverted h osd composite h v inverted v osd v osd h osd pal ntsc fig. 236: programming sync format of h osd and v osd ccz 3005k preliminary data sheet 38 micronas 2.17. infrared input programmed to work in special input mode, p35 (bit 5 of port 3) may be used to detect infrared signals. the hardware of the infrared input is designed to support software decoding of different infrared signals. in most infrared telegrams, data are coded as pulse sequences or different logical levels that follow start edges or pulses. a logical `0' differs from a `1' in the availability of a defined logical level (`0' or `1') during specific time slots after this start edge or pulse, in defined delays between the start edge (or pulse) and a followed data pulse or a logical level during some time after the start edge. the hardware of the ccz 3005k offers the possibility to program two time values that define the moments when the infrared signal is scanned. two values of 0 to 14 as nibbles in the 8-bit `ir sample times' register determine two delays starting at the active infrared signal edge. the value 15 for `ir sample times' is not allowed. with bit 5 in the `ir control and status' register, the step size of the sample time value is programmable: with bit 5 set to `0', the step size is 85 m s and values from 0 to 14 x 85 m s = 1.19 ms are determined. with bit 5 = `1', the step size is 170 m s and the values are from 0 to 14 x 170 m s = 2.38 ms. the absolute delay error is +1 lsb, for exam- ple. with step size = 85 m s and sample time value = 2, the delay is in the range between 170 m s and 255 m s. start edge start pulse infrared telegram data pulse data pulse delay time time slot data = `1' data = `0' a) fig. 237: part of an infrared telegram data = `0' b) data = `1' data = `0' c) data = `1' t1 t2 sample time fig. 238: examples of differently coded infrared signals ccz 3005k preliminary data sheet 39 micronas in the `ir control and status' register, it is programmable whether a rising or falling edge has to be evaluated as active infrared signal start edge and whether infrared detection has to generate interrupts. either the active in- frared signal start edge or the detection of the higher of both programmed sampling times (`both samples tak- en') may generate an interrupt. the result of scanning is delivered in the `ir control and status' register. sample clock divider 4-bit counter n.c. bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n.c. n.c. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 ccz data bus clr (from timer) s r clr edge detector bits 0 to 3 bits 4 to 7 ir in osc/2 ccz data bus `ir control and status' write (addr. 2f5h) t sample1 t sample2 ccz data bus ir `sample times' write (addr. 2f6h) irq source: both samples taken/ir in active edge n.c. n.c. n.c. irq (cpu) irq active/inactive active ir in trigger edge selection sample t2 sample t1 both samples taken ir in edge found timer caused interrupt ir in pin level `ir control and status' read (addr. 2f5h) fig. 239: block diagram of infrared input q q q clr q q `1' `1' ir in sample rate ccz 3005k preliminary data sheet 40 micronas 2.17.1. infrared detection status infrared status register as part of the `ir control and status register' (addr. 2f5h): bit 6 = ir in pin level at moment t2 bit 4 = interrupt source: if `1': timer caused interrupt (2.048 ms if system clock = 12 mhz) bit 3 = if `1': ir in active start edge found bit 2 = ir in pin level (direct, as if read by standard input port) bit 1 = if `1': both samples taken bit 0 = ir in pin level at moment t1 bit 4 `interrupt source' is set to `0' after every read access to the `ir control and status' register, while bits 0, 1, 3 and 6 become `0' after reading the status with a `1' in bit 1, indicating that both samples have been taken, i.e.,: bits 0 and 6 are valid. to trigger the infrared signal start edge only, and not the data edges as well, the sample counters are not retriggerable. they start with the first occurrence of the edge they are programmed for (rising or falling) and become sensitive for the next start after the higher of both sampling times has passed (`both samples taken'), so, in the worst case, after 2.55 ms. 2.17.2. infrared detection control by writing to the `ir control and status' register, the ac- tive start edge of the ir in signal can be determined: bit 7 = `0': use first detected falling edge, bit 7 = `1': use first detected rising edge of the ir in signal to start the two sample timers. if and what can generate an interrupt is also selectable: bit 6 = `0': disable irq bit 6 = `1': enable irq . this irq can be caused by the chosen active edge (se- lected with bit 7) or if both samples are taken, (in parallel to bit 1 of the status register): bit 3 = `0': use active ir in edge, bit 3 = `1': generate irq when both samples are taken (same signal as in status register). bit 5 of the control part of the `ir control and status' reg- ister determines the step size for the programmable sample rate: bit 5 = `0': step size = 85 m s, bit 5 = `1': step size = 170 m s. programming the `ir control and status' register may already cause an irq after having been enabled by the processors' command `cli' before. also the `cli' that follows the write to the register may cause the irq if it was not cleared by reading this register before (refer to chapter 2.19.). 2.17.3. sample times with two nibbles in the `ir sample times' register (addr. 2f6h), two moments for sampling the ir in signal are programmable. the values between 0 and 14 have to be multiplied with either 85 m s or 170 m s, depending on how bit 5 of the `ir control and status' register is pro- grammed. thus values between 0 and 14 x 170 m s = 2.38 ms are programmable. ccz 3005k preliminary data sheet 41 micronas 2.18. timer the irq input is accessed by a free-running timer with 2.048 ms (f system = 6 mhz). as soon as an irq has been generated, each further irq depends on the reading of the infrared register, which has to be done first and which also provides information on the irq-source (ir-input is also an irq-source) (see fig. 239). the readable system counter is derived from the 16-bit prescaler. although this counter cannot be preset, it can be read. its value is incremented by 1 with every f2 clock. overrun occurs from ffffh to 0000h. to get a definite value, the msbyte is copied into a register that can later be read out (204h) while the lsbyte (203h) is read; i.e., the msbyte is latched by reading the lsbyte. address function 203h(r) lsbyte timer, save msbyte 204h(r) msbyte (saved value) f system 8 bit 8 bit latch data-bus rd_timer_low fig. 240: readable timer rd_timer_high 2.19. interrupt system the cpu 65c02 contains two interrupts. interrupt sources irq ir-interface, timer nmi v sync , caption line the irq is mask-programmable via software. the in- frared register detects which of the two sources has trig- gered the interrupt. the ir interface can also separately be switched off as int source. as soon as an irq is gen- erated, it is disabled until the `ir control and status' reg- ister is read. if the `ir control and status' register is read while an enabled irq is pending, the irq can be ig- nored. the software is responsible for starting the irq function if an irq is detected. the nmis also become disabled with occurrence. the sources are distinguished by testing the v sync -input, bit 7 of the `window logic control register 1'. to get a fur- ther nmi, a write with any value to the `nmi return' register (addr. 236h) has to be executed immediately before the artio of the nmi service routine. as writes to the `nmi return' register are registered, the first write should not occur before the first occurrence of an nmi. therefore it is not advisable to execute a write to the `nmi return' during initialization, because in that case, the first nmi does not block itself and the second nmi may be nested! a write (of any data) to the `nmi return' register enables a succeeding nmi with the next processor sync signal. the nmi for both the v sync and caption line is disabled until a first write to the `closed caption line number' register (address 23eh) occurs. fig. 241: int system ccz 3005k s r q `ir control and status'(addr. 2f5h) read irq nmi cpu ir input 2.048 ms v sync caption_line s r q `nmi-return' register (addr. 236h) write ccz 3005k preliminary data sheet 42 micronas 3. specifications 3.1. outline dimensions fig. 31: 52-pin plastic shrink dual-in-line package (psdip52) weight approximately 5.5 g dimensions in mm 16.3 1 0.28 0.06 14 0.1 15.6 0.1 126 27 52 47.0 0.1 0.6 0.2 4.0 0.1 2.8 0.2 1.778 1 0.05 25 x 1.778 = 44.4 0.1 0.48 0.06 spgs703000-1(p52)/1e 3.2. pin connections and short descriptions x = obligatory; connect as described in circuit diagram pin no. pin name type connection short description psdip 52-pin (if not used) 1 p34 in/out x port 3, bit 4 2 p35 /ir in in/out x or output signal of ext. infrared receiver port 3, bit 5 or infrared signal input 3 p36 in/out x port 3, bit 6 4 p37/pwm6 in/out x port 3, bit 7 or pulse width modulator (d/a converter) output no. 6 5 p00 in/out x port 0, bit 0 6 p01 in/out x port 0, bit 1 7 p02 in/out x port 0, bit 2 8 p03 in/out x port 0, bit 3 9 p04/v osd in/out x port 0, bit 4 or vertical synchronization output of internal h&v sync generator 10 p05/h osd in/out x port 0, bit 5 or horizontal synchronization out- put of internal h&v sync generator 11 p06 in/out x port 0, bit 6 preliminary data sheet ccz 3005k 43 micronas pin connections and short descriptions, continued pin no. pin name type connection short description psdip 52-pin (if not used) 12 p07 in/out x port 0, bit 7 13 video in in external video source signal input for external video signal (for closed caption data decoding) 14 slicer capacitance in/out slicer capacitor connection for slicer capacitor 15 porqtest in gnd test pin (usable by manufacturer only) 16 adc0 in external analog analog converter input no. 0 17 adc1 in analog signal analog converter input no. 1 18 adc2 in analog converter input no. 2 19 adc3 in analog converter input no. 3 20 adc4 in analog converter input no. 4 21 gnda supply gnd ground connection (same as digital ground) 22 v supa supply +5v analog analog power supply 23 half-video out half-video control input of external rgb stage half-video control output of internal osd cir- cuit 24 b out out blue input of external rgb stage blue color control output of internal osd circuit 25 g out out green input of external rgb stage green color control output of internal osd cir- cuit 26 r out out red input of external rgb stage red color control output of internal osd circuit 27 fast blank out fast blank input of ex- ternal rgb stage fast blank control output of internal osd cir- cuit 28 h sync1 in h sync output of external osd stage horizontal synchronization input of internal osd circuit and closed caption detection cir- cuit 29 v sync in v sync output of external osd stage vertical synchronization input of internal osd circuit ccz 3005k preliminary data sheet 44 micronas pin connections and short descriptions, continued pin no. pin name type connection short description psdip 52-pin (if not used) 30 p10 / im 2 -dat / i 2 c 2 -sda in/out x or i 2 c-data line of exter- nal device(s) port 1, bit 0 or i 2 c-data 31 p11 / im 2 -clk / i 2 c 2 -scl in/out x or im-ident line of exter- nal device(s) port 1, bit 1 or i 2 c-clock 32 p12 / im-id in/out port 1, bit 2 or im-ident 33 p13 / im 1 -dat / i 2 c 1 -sda in/out x or im-data resp. i 2 c- data line of external de- vice(s) port 1, bit 3 or im-data resp. i 2 c - data 34 p14 / im 1 -clk / i 2 c 1 -scl in/out x or im-clock resp. i 2 c- clock line of external de- vice(s) port 1, bit 4 or im-clock resp. i 2 c - clock 35 reset in/out external re- set signal ccu reset signal 36 xtal1 in ccu clock crystal crystal connector 37 xtal2 out cr y stal crystal connector 38 gnd supply gnd ground connection 39 v sup supply +5 v (digital) power supply (digital) 40 test in gnd test pin (usable by manufacturer only) 41 p20 / pwm0 in/out x or low pass filter and analog port 2, bit 0 or pulse width modulator (d/a converter) output no. 0 42 p21 / pwm1 in/out an d ana l og input of ex- ternal device port 2, bit 1 or pulse width modulator (d/a converter) output no. 1 43 p22 / pwm2 in/out port 2, bit 2 or pulse width modulator (d/a converter) output no. 2 44 p23 / pwm3 in/out port 2, bit 3 or pulse width modulator (d/a converter) output no. 3 45 p24 / pwm4 in/out port 2, bit 4 or pulse width modulator (d/a converter) output no. 4 46 p25 / pwm5 in/out port 2, bit 5 or pulse width modulator (d/a converter) output no. 5 preliminary data sheet ccz 3005k 45 micronas pin connections and short descriptions, continued pin no. pin name type connection short description psdip 52-pin (if not used) 47 p26 in/out x port 2, bit 6 48 p27 / h sync1 in/out x or h sync output of ex- ternal osd stage port 2, bit 7 or horizontal synchronization input of internal osd circuit and closed cap- tion detection circuit 49 p30 in/out x port 3, bit 0 50 p31 in/out x port 3, bit 1 51 p32 in/out x port 3, bit 2 52 p33 in/out x port 3, bit 3 3.3. pin descriptions pin numbers refer to the 52-pin psdip package. the functions of some port pins can be changed to either `standard mode' or `special mode' by setting the specific bits in their mode registers. pin 1: p34: bit 4 of port 3, connection depends on application pin 2: p35 or ir in : in standard mode : bit 5 of port 3, connection depends on application in special mode : infrared signal input, to connect with the output of the infrared receiver pin 3: p36: bit 6 of port 3, connection depends on application pin 4: p37 or pwm6: in standard mode : bit 7 of port 3, connection depends on application in special mode : pwm (d/a converter) output no. 6 pin 5: p00: bit 0 of port 0, connection depends on application pin 6: p01: bit 1 of port 0, connection depends on application pin 7: p02: bit 2 of port 0, connection depends on application pin 8: p03: bit 3 of port 0, connection depends on application pin 9: p04 or v osd : in standard mode : bit 4 of port 0, connection depends on application in special mode : vertical synchronization output of internal h&v sync generator pin 10: p05 or h osd : in standard mode : bit 5 of port 0, connection depends on application in special mode : horizontal synchronization output of internal h&v sync generator pin 11: p06 bit 6 of port 0 connection depends on application pin 12: p07 bit 7 of port 0 connection depends on application pin 13: video in : video signal input to connect the closed caption data signal ccz 3005k preliminary data sheet 46 micronas pin 14: slicer capacitance: slicer capacitance connector, with the other side of the capacitor to gnd pin 15: gnd (porqtest): has to be connected to gnd (usable by manufacturer only) pin 16: adc0: analog to digital converter input no. 0 pin 17: adc1: analog to digital converter input no. 1 pin 18: adc2: analog to digital converter input no. 2 pin 19: adc3: analog to digital converter input no. 3 pin 20: adc4: analog to digital converter input no. 4 pin 21: gnda: analog ground (gnd) input pin 22: v supa : analog voltage supply (+5v) input pin 23: half-video: half-video output signal, to control the osd output stage working in half-video mode pin 24: b out: blue intensity output, to control the osd output stage pin 25: g out green intensity output, to control the osd output stage pin 26: r out : red intensity output, to control the osd output stage pin 27: fast blank: fast blank output, to enable the osd output stage using the ccz's r, g, b outputs pin 28: h sync1 : one of two available horizontal synchronization signal inputs to connect with the horizontal synchronization output signal of the external osd source pin 29: v sync : vertical synchronization input signal to connect with the horizontal synchronization output signal of the external osd source. pin 30: p10 or im 2 -dat resp . i 2 c 2 -sda: in standard mode: bit 0 of port 1, connection depends on application in special mode: im-bus data or i 2 c-bus data, to connect with the same signal(s) of external device(s). it depends on the register that was written to (im-bus control or i 2 c-bus control) whether the terminal is used as im-bus or as i 2 c-bus data line. pin 31: p11 or im 2 -clk resp. i 2 c 2 -scl: in standard mode: bit 1 of port 1, connection depends on application in special mode: im-bus clock or i 2 c-bus clock, to connect with the same signal(s) of external device(s). it depends on the register that was written to (im- bus control or i 2 c-bus control register) whether the terminal is used as im-bus or as i 2 c-bus clock line. pin 32: p12 or im-id: in standard mode: bit 2 of port 1, connection depends on application in special mode: im-bus ident, to connect with the same signal(s) of external device(s). pin 33: p13 or im 1 -dat resp. i 2 c 1 -sda: in standard mode: bit 3 of port 1, connection depends on application in special mode im-bus data or i 2 c-bus data, to connect with the same signal(s) of external device(s). it depends on the register that was written to (im-bus control or i 2 c-bus control) whether the terminal is used as im-bus or as i 2 c-bus data line. pin 34: p14 or im 1 -clk resp. i 2 c 1 -scl: in standard mode: bit 4 of port 1, connection depends on application in special mode: im-bus clock or i 2 c-bus clock, to connect with the same signal(s) of external device(s). it depends on the register that was written to (im- bus control or i 2 c-bus control register) whether the terminal is used as im-bus or as i 2 c-bus clock line. pin 35: reset : ccz reset pin to connect with a signal to reset the ccz. pin 36: xtal1: first crystal connector. preliminary data sheet ccz 3005k 47 micronas pin 37: xtal2: second crystal connector pin 38: gnd: digital ground (gnd) input pin 39: vsup: digital voltage supply (+5v) input pin 40: test: test input, leave vacant or connect with gnd pin 41: p20 or pwm0: in standard mode: bit 0 of port 2, connection depends on application in special mode: pwm (d/a converter) output no. 0 pin 42: p21 or pwm1: in standard mode: bit 1 of port 2, connection depends on application in special mode: pwm (d/a converter) output no. 1 pin 43: p22 or pwm2: in standard mode: bit 2 of port 2, connection depends on application in special mode: pwm (d/a converter) output no. 2 pin 44: p23 or pwm3: in standard mode: bit 3 of port 2, connection depends on application in special mode: pwm (d/a converter) output no. 3 pin 45: p24 or pwm4: in standard mode: bit 4 of port 2, connection depends on application in special mode: pwm (d/a converter) output no. 4 pin 46: p25 or pwm5: in standard mode: bit 5 of port 2, connection depends on application in special mode: pwm (d/a converter) output no. 5 pin 47: p26: bit 6 of port 2, connection depends on application pin 48: p27 or h sync2 : in standard mode: bit 7 of port 2, connection depends on application in special mode: one of two available horizontal synchronization signal inputs to connect with the horizontal synchronization output signal of the external osd source pin 49: p30: bit 6 of port 3, connection depends on application pin 50: p31: bit 1 of port 3, connection depends on application pin 51: p32: bit 2 of port 3, connection depends on application pin 52: p33: bit 3 of port 3, connection depends on application 3.4. pin configuration p12/im-id p14/im 1 -clk/i 2 c 1 -scl p13/im 1 -dat/i 2 c 1 -sda p11/im 2 -clk/i 2 c 2 -scl p10/im 2 -dat/i 2 c 2 -sda xtal2 v supa adc2 adc1 slicer capacitance p02 video in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 p00 p01 p03 p06 p30/average p25/pwm5 p24/pwm4 p23/pwm3 p21/pwm1 gnd (test) p20/pwm0 p32/sync tip p22/pwm2 p37/pwm6 p26/ext. slicer p33/cc line 21 22 23 24 25 26 27 28 29 30 31 32 half-video fig. 32: 52-pin psdip package, top view ir in /p35 p07 fast blank xtal1 gnd (porqtest) adc0 adc3 adc4 p27/h sync2 v sync h sync1 b out g out r out reset v sup gnda gnd a2 output/p34 ir in output/p36 p31/run-in key p04/v osd p05/h osd ccz 3005k preliminary data sheet 48 micronas 3.5. pin circuits pin numbers refer to 52-pin psdip package. pad v sup v sup fig. 33: push-pull i/o p30 to p37: pins 1 to 4 and 49 to 52 p20 to p27: pins 41 to 48 p12: pin 32 p00 to p07: pins 5 to 12. pad v sup fig. 34: open drain i/o p10, p11, p13, p14: pins 30, 31, 33, 34 pad v sup v sup fig. 35: push-pull output half-video and fast blank: pins 23, 27. v sup pad fig. 36: xtal output xtal2: pin 37 pad v sup fig. 37: analog input xtal1: pin 36 adc0 to adc4: pins 16 to 20 pad v sup fig. 38: schmitt-trigger input with pull-down resistor porqtest: pin 15 test: pin 40 v sup 10 k fig. 39: video in , slicer capacitance video in : pin 13 slicer capacitance: pin 14 pin 14 pin 13 slicer capacitance v sup video in run-in key preliminary data sheet ccz 3005k 49 micronas v sup fig. 310: schmitt-trigger input v sync : pin 29 h sync1 : pin 28 pad v sup f osc < 500 khz power-on watchdog fig. 311: reset reset : pin 35 pad fig. 312: pin circuit rgb-out dr0\i dr33\i dr66\i dr100\i v ref33 v ref66 v sup v sup\g cpad\i v sup color 1 1 1 v sup rgb pins in standby bit `0' `hardware control register' ccz 3005k preliminary data sheet 50 micronas 3.6. electrical characteristics all voltages refer to ground 3.6.1. absolute maximum ratings symbol parameter pin min. max. unit t a ambient operating temperature 0 70 c t s storage temperature 40 125 c v sup supply voltage 39 0.5 6 v v supa analog supply voltage 22 0.5 6 v i sup supply current 39 50 50 ma i supa analog supply current 22 50 50 ma v i input voltage 1 to 12, 23, 27 to 34, 41 to 52 0.3 v sup +0.3 v v ia analog input voltage 16 to 20 0.3 v supa +0.3 v i o output current 1 to 12, 23, 27 to 34, 41 to 52 5 5 ma i or,g,b r, g, b output current 24 to 26 1.6 1.6 ma i oa analog output current 13, 14, 37 2 00 200 m a stresses beyond those listed in the aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating conditions/characteristicso of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. preliminary data sheet ccz 3005k 51 micronas 3.6.2. recommended operating conditions at t a = 0 to 70 c, fxtal = 12.0 mhz symbol parameter pin min. typ. max. unit v sup 1) supply voltage (digital) 39 4.75 5.0 5.25 v v supa 1) analog supply voltage 22 4.75 5.0 v sup v v video video input level 13 1.0 2.0 v pp v syncl sync input low voltage 28, 29, 48 0.8 v v synch sync input high voltage 48 3.0 v xtal1 duty clock input high/low ratio 36 0.9 1.0 1.1 xtal1 tran clock rise/fall time 12.5 ns v il 2) input low voltage all port pins 1to12 0.8 v v ih 2) input high voltage 1 to 12 , 30 to 34, 41 to 52 3.0 v rgb analog outputs r load external load resistor 24 to 26 20 k w c load external load capacitor 20 pf im-bus/i 2 c outputs r load external load resistor 30 to 34 2 k w c load external load capacitor 100 pf sync inputs t hsync pulse width of horizontal sync 28, 48 6 t osc t vsync pulse width of vertical sync 29 6 t osc 1) gnd and gnda are short-circuited on chip. both of these pins should be hardwired to common gnd plane. capacitors should be used as near as possible to the v sup and v supa pins against gnd to minimize supply voltage disturbance. v supa must not exceed v sup ! 2) all port pins have schmitt-trigger inputs with a hysteresis of about 0.9 v. ccz 3005k preliminary data sheet 52 micronas 3.6.3. recommended crystal characteristics symbol parameter min. typ. max. unit test cond. f xtal parallel resonance frequency for ntsc 11.5 12.083712 12.5 mhz c l = 17.5 pf f xtal parallel resonance frequency for pal, secam 11.5 12.000000 12.5 mhz c l = 17.5 pf df p/ fp frequency deviation versus temperature and aging 100 ppm r r series resistance 40 ohm c xtal1 = c xtal2 = 22 pf 1 pf, c stray 2 pf c 0 shunt capacitance 5.5 7 pf c 1 motional capacitance 0.015 0.025 pf preliminary data sheet ccz 3005k 53 micronas 3.6.4. dc characteristics at t a = 0 to 70 c, v sup = 4.75 to 5.25 v, f xtal = 12 mhz for min./max. values at t a = 60 c, v sup = 5 v, f xtal = 12 mhz for typical values symbol parameter pin no. min. typ. max. unit test conditions i sup 1) supply current (digital) 39 22 50 ma no loads on outputs i supa 1) analog supply current 22 1 ma no loads on outputs i supastby 1) 2) analog standby supply current 1 m a no loads on outputs adc inputs i lia 1) analog input leakage current 16 to 20 1 1 m a gnd v in v sup inputs i li leakage current 1 to 14, 23, 27 to 35, 41 to 52 1 1 m a gnd v in v sup rgb analog outputs r i internal resistance 24 to 26 2 k w (guaranteed by design) port outputs v ol output low voltage 1 to 12, 30 to 34 0.4 v i out = 2 ma v oh output high voltage 30 to 34 , 41 to 52 v sup 0. 5 v i out = 1 ma port 1 in special mode (i 2 c-bus) v od output low voltage in open drain configuration 30, 31, 33, 34 0.4 v i out = 5 ma reset pin v rol reset pin output low voltage 35 0.4 v i out = 2 ma 1) gnd and gnda are short-circuited on chip. both of these pins should be hardwired to common gnd plane. capacitors should be used as near as possible to the v sup and v supa pins against gnd to minimize supply voltage disturbance. v supa must not exceed v sup ! 2) adc hardware disabled with bit 3 in `hardware control' register, address 209h, set to `0'. ccz 3005k preliminary data sheet 54 micronas 3.6.5. dc parameters i 2 c-bus master interface the input and output parameters of the i 2 c-bus interface (clock and data) are designed according to the micronas specification for port and im-bus pins (the interface can also be operated as im-bus interface). the differences are symbol meaning micronas i 2 c specification v il input low voltage max. 0.8 v max. 1.5 v v ih input high voltage min. 2.5 v min. 3 v v ol output low voltage 0.4 / 5 ma 0.4 v / 3 ma the micronas parameters are equivalent to software i 2 c-bus solutions using port-lines for the bus. in applications with series resistors in the clock or data line these differences may become important. capacities on any of these pins should not exceed 100 pf. higher capacities could effect higher disturbances. table 29: ac characteristics symbol parameter min. typ. max. unit test conditions t ph2 cpu cycle time 2 t osc 3.6.6. a/d converter characteristics symbol parameter min. typ. max. unit test conditions resolution 8 bits absolute accuracy 4 lsb t conv conversion time 68 t osc v ia analog input voltage v supa v dw min minimum digital value 00h v ia preliminary data sheet ccz 3005k 56 micronas 5. register description (x corresponds to undefined for read, no function for write.) do not access any other addresses in page 2 than men- tioned here. fill unused register bits with `0' to be software-compatible with other versions of ccz 3005k. 0200h system clock prescaler register (use not recommended, as not tested) bit reset read write 7 to 0 0 x divisor value 1, determines f system : f system = f xtal / 2* (divisor value+1) 0201h ccz control register bit reset read write 7 to 3 x 1 2 `0' = rom external , `1' = rom internal `0' = rom external , `1' = rom internal 1 `0' = ram external , `1' = ram internal `0' = ram external , `1' = ram internal 0 `0' = cpu external , `1' = cpu internal `0' = cpu external , `1' = cpu internal 0202h watchdog control and status register bit reset read write 7 x x 6 x x 5 x x 4 x x 3 x x 2 x x 1 x test 0 x `0' = reset was generated by watchdog copied from addr. fff9h during reset (do not use settings n < 2!!) f system . 65536 with f system = 6 mhz: n = n min = 2 ? t wdmin = 32.768 ms n = n max = 255 ? t wdmax = 2.796 s min. d n = 1 ? min. d t wd = 10.922666 ms t wd 1 = n (the watchdog is disabled after reset) preliminary data sheet ccz 3005k 57 micronas 0203h system counter ls byte bit reset read write 7 0 bit 7 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 bit 0 x 0204h system counter ms byte bit reset read write 7 0 bit 15 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 bit 8 x 0209h hardware control register bit reset read write 7 to 6 x x x 5 0 x port buffers, half video and fast blank output control: `0' = normal, `1' = current-controlled 4 x x x 3 0 x `1' = enable adc hardware, `0' = adc hardware in standby 2 to 1 x x x 0 0 x `1' = rgb hardware in standby, output pins tristate counter value low byte counter value high byte (latched by reading counter value low byte) preliminary data sheet ccz 3005k 58 micronas 0236h nmi-return register bit reset read write 7 to 0 x x x enables the succeeding nmi with the next processor sync signal (nmis automatically become disabled with occurrence.) 0237h window logic control register 2 bit reset read write 7 to 4 x x x 3 0 selected hsync input: `0': h sync1 , `1': h sync2 hsync input select: `0': h sync1 , `1': h sync2 2 0 `0' = video peak clamp, `1' = video gated clamp `0' = video peak clamp, `1' = video gated clamp 1 0 detect video: `0' = run-in key enabled, `1' = run-in key disabled detect video: `0' = enable run-in key, `1' = disable run-in key 0 0 `0' = 3 line interrupt disabled, `1=' 3 line interrupt enabled `0' = disable 3 line interrupt, `1' = enable 3 line interrupt preliminary data sheet ccz 3005k 59 micronas 0238h window logic control register 1 bits reset read write 7 x `0': vsync inactive, `1': vsync active x 6 1 `0' = line counter inactive, `1' = line counter active `0' = deactivate line counter, `1' = activate line counter 5 0 `0' = cpu_so input disabled, `1' = cpu_so input enabled `0' = disable cpu_so input , `1' = enable cpu_so input 4 1 `0' = halfdot rounding disabled, `1' = halfdot rounding enabled `0' = disable halfdot rounding, `1' = enable halfdot rounding 1) 3 x `0' = osd active , `1' = osd inactive x 2 1 active edge of vsync: `0': rising, `1': falling active edge of vsync: `0': rising, `1': falling 1 1 active edge of hsync for acquisition: `0': rising, `1': falling active edge of hsync for acquisition: `0': rising, `1': falling 0 1 active edge of hsync for osd: `1': rising, `0': falling active edge of hsync for osd: `1': rising, `0': falling 1) halfdot rounding may be active during field 2 (even field) only, so software has to toggle this bit with every active v sync edge. halfdot rounding not defined for horizontal start position (reg. 0262h) less than 6 and greater than 46. 0239h sync tip clamp start value register bit reset read write 7 to 0 1 synctip start value synctip start value 023ah sync tip clamp end value register bit reset read write 7 to 0 1 synctip stop value (duration of synctip: = (reg23a reg239)*4/pxtal) synctip stop value (duration of synctip: = (reg23a reg239)*4/pxtal) 023bh run-in key start value register bit reset read write 7 to 0 1 run-in key start value run-in key start value preliminary data sheet ccz 3005k 60 micronas 023ch run-in key end value register bit reset read write 7 to 0 1 run-in key stop value (duration of run-in key: = (reg23c reg239b)*4/pxtal) run-in key stop value (duration of run-in key: = (reg23c reg239b)*4/pxtal) 023dh vertical sync phase value register (field 1/field 2 determination) bit reset read write 7 to 0 x vertical sync phase value x 023eh closed caption line number bit reset read write 7 to 0 1 number of closed caption line number of closed caption line (both v sync and caption line interrupt (nmi) is- disabled until a first write to this register occurs). 023fh captured data register bit reset read write 7 to 0 x captured data x 0250h pwm0 data register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter value 0251h pwm1 data register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter value preliminary data sheet ccz 3005k 61 micronas 0252h pwm2 data register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter value 0253h pwm3 data register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter value 0254h pwm4 data register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter value 0255h pwm5 data register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter value 0256h pwm6 data low register bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x pwm counter low value 0257h pwm6 data high register bit reset read write 7 to 0 0 x pwm counter high value (writing this register transfers the com- plete 14bit value into the pwm6 count- er) preliminary data sheet ccz 3005k 62 micronas 0260h osd first active scan line (9 bits) of osd window (set high bits to `1') (vertical start of osd window) bit reset read write 7 to 0 0 x number of the first displayed osd-scan- line (the first access defines the high bit (bit 0), the second access defines the low byte of the number; two accesses are always required) 0261h osd last active scan line (9 bits) of osd window (set high bits to `1') (vertical stop of osd window) bit reset read write 7 to 0 0 x number of the last displayed osd-scan line (the first access defines the high bit (bit 0), the second access defines the low byte of the number; two accesses are always required) 0262h osd horizontal start position of osd window (in character steps) bit reset read write 7 0 x x 6 0 x x 5 to 0 0 x osd-x-start position (must be greater than 1) (don't use values less than 6 and greater than 46 if halfdot rounding is enabled (bit 4 in register 0238h = window logic con- trolreg_1 set to `1') preliminary data sheet ccz 3005k 63 micronas 0263h osd control register bit reset read write 7 0 x `1' = enable nci decoder (telecaption mode of the osd), `0' = enable standard osd mode 6 0 x `1' = display on `0' = display off 5 0 x `0' = flash on, `1' = flash off (foreground= background) 4 0 x `0' = font size 13x8 (ntsc), `1' = 15x8 (pal) 3 to 0 0 x start scan line: selects the first scan line of the first character row. this capability allows the smooth scrolling feature to look correct at the top of the window. 0264h osd text start address register bit reset read write 7 to 0 0 x start address of text to be displayed (the first access defines the high byte, the second access defines the low byte of the address; two accesses are always required) 0265h osd separate colored line (9 bits) (set high bits to `1') bit reset read write 7 to 0 0 x number of second color scan line (the first access defines the high bit, (bit 0); the second access defines the low byte of the number; two accesses are always required) 0266h osd separate color definition register (bits 0 to 6: same format as attribute `color') bit reset read write 7 0 x `0' = fastblank active low, `1' = fastblank active high 6 0 x `1'= color 0 is replaced by transparent 5 to 3 0 x value 0 to 7 defining background color (color 0 to color 7) 2 to 0 0 x value 0 to 7 defining foreground color (color 0 to color 7) preliminary data sheet ccz 3005k 64 micronas 0267h osd color palette red bit reset high low (2nd access) (1st access) read write 7 11 x color 7 6 11 x color 6 5 11 x color 5 4 11 x color 4 3 00 x color 3 2 00 x color 2 1 00 x color 1 0 00 x color 0 0268h osd color palette green bit reset high low (2nd access) (1st access) read write 7 11 x color 7 6 11 x color 6 5 00 x color 5 4 00 x color 4 3 11 x color 3 2 11 x color 2 1 00 x color 1 0 00 x color 0 0269h osd color palette blue bit reset high low (2nd access) (1st access) read write 7 11 x color 7 6 00 x color 6 5 11 x color 5 4 00 x color 4 3 11 x color 3 2 00 x color 2 1 11 x color 1 0 00 x color 0 (the first access de- fines the low bits, the second access defines the high bits of the col- ors intensity, two ac- cesses are always re- quired) (the first access de- fines the low bits, the second access defines the high bits of the col- ors intensity, two ac- cesses are always re- quired) (the first access de- fines the low bits, the second access defines the high bits of the col- ors intensity, two ac- cesses are always re- quired) preliminary data sheet ccz 3005k 65 micronas 026ah osd half-video control register bit reset read write 7 to 1 x x x 0 0 x `0'= disable half-video (half-video output pin level=`0') `1'=enable half-video 026eh osd font1, font2 start addresses (32 bits) bit reset read write 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 x 026fh osd horizontal start adjust and display options bit reset read write 7 0 x enable horizontal shadow 6 0 x blank display 5 0 x `0' = display mode 0 `1' = display mode 1 4 0 x `0' = single underline in scan line 11 `1' = single underline in scan line 12 (works with 13 x 8 font only) 3 x x x 2 1 x 1 1 x 0 1 x 0270h cursor pointer, low byte bit reset read write 7 to 0 0 x start address of the cursor definition bit- map (low one of two bytes) start address of font1 and font2 (the first access defines the high byte, the second access the low byte of the font1 address; the third access defines the high byte, the fourth access the low byte of the font2 address; there are always 4 accesses required!) x-fine adjust preliminary data sheet ccz 3005k 66 micronas 0271h cursor pointer, high byte bit reset read write 7 to 0 0 x start address of the cursor definition bit- map (high one of two bytes) 0272h cursor xposition, low byte bit reset read write 7 to 0 1 xposition (horizontal start) of cursor (least significant eight of nine bits) xposition (horizontal start) of cursor (least significant eight of nine bits) 0273h cursor xposition, high byte bit reset read write 7 0 cursor on/offswitch: '0': cursor off '1': cursor on cursor on/offswitch: `0': cursor off `1': cursor on 6 to 4 0 cursor color mask 2 cursor color mask 2 3 to 1 0 cursor color mask 1 cursor color mask 1 0 1 xposition (horizontal start) of cursor (most significant of nine bits) xposition (horizontal start) of cursor (most significant of nine bits) 0274h cursor yposition, low byte bit reset read write 7 to 0 0 yposition (vertical start) of cursor (least significant eight of nine bits) yposition (vertical start) of cursor (least significant eight of nine bits) 0275h cursor yposition, high byte bit reset read write 7 0 cursor transparentswitch: `0': transparent off `1': transparent on cursor transparentswitch: `0': transparent off `1': transparent on 6 0 cursor halfvideoswitch: '0': half video off '1': half video on cursor halfvideoswitch: `0': half video off `1': half video on 5 0 cursor fast blank polarity: '0': active low '1': active high cursor fast blank polarity: `0': active low `1': active high 4 x x x 3 to 1 0 cursor color mask 3 cursor color mask 3 0 1 yposition (vertical start) of cursor (most significant of nine bits) yposition (vertical start) of cursor (most significant of nine bits) preliminary data sheet ccz 3005k 67 micronas 0276h field detector osd (field 1/field 2 determination) bit reset read write 7 to 0 x vertical sync phase value x 0277h horizontal sync tracking speed bit reset read write 7 to 5 0 x x 4 to 0 0 x tracking speed for horizontal sync timer 0278h vertical sync tracking speed bit reset read write 7 to 5 0 x x 4 to 0 0 x tracking speed for vertical sync timer 0279h h&v sync generator mode bit reset read write 7 0 x x 6 0 x `0' = normal v osd output `1' = inverted v osd output 5 0 x `0' = normal h osd output `1' = inverted h osd output 4 0 x `0' = vertical tracking disabled `1' = vertical tracking enabled 3 0 x `0' = horizontal tracking disabled `1' = horizontal tracking enabled 2 0 x `0' = separate v osd & h osd output `1' = composite sync output 1 0 x `0' = pal mode `1' = ntsc mode 0 1 x `0' = selftimed sync mode `1' = external sync mode preliminary data sheet ccz 3005k 68 micronas 0280h port0 mode register bit reset read write 7 0 x `0' = normal mode, `1' = special mode 6 0 x `0' = normal mode, `1' = special mode 5 0 x `0' = normal mode, `1' = special mode (h osd output) 4 0 x `0' = normal mode, `1' = special mode (v osd output) 3 0 x `0' = normal mode, `1' = special mode 2 0 x `0' = normal mode, `1' = special mode 1 0 x `0' = normal mode, `1' = special mode 0 0 x `0' = normal mode, `1' = special mode 0281h port0 tristate register bit reset read write 7 to 0 1 x `0' = output conducting, `1' = output tristate 0282h port0 input data/output register bit reset read write 7 to 0 0 port0 data port0 data 0284h port1 mode register bit reset read write 7 to 5 x x (not available) x (not available) 4 0 x `0' = normal mode, `1' = special mode (im 1 -clk/i 2 c 1 -scl) 3 0 x `0' = normal mode, `1' = special mode (im 1 -dat/i 2 c 1 -sda) 2 0 x `0' = normal mode, `1' = special mode (im-id) 1 0 x `0' = normal mode, `1' = special mode (im 2 -clk/i 2 c 2 -scl) 0 0 x `0' = normal mode, `1' = special mode (im 2 -dat/i 2 c 2 -sda) preliminary data sheet ccz 3005k 69 micronas 0285h port1 tristate register (only 5 bits available) bit reset read write 4 to 0 1 x `0' = output conducting, `1' = output tristate 0286h port1 data register (only 5 bits available) bit reset read write 4 to 0 0 port1 data port1 data 0288h port2 mode register bit reset read write 7 0 x `0' = normal mode, `1' = special mode (h sync2 input) 6 0 x `0' = normal mode, `1' = special mode (ext. slicer) 5 0 x `0' = normal mode, `1' = special mode (pwm5 output) 4 0 x `0' = normal mode, `1' = special mode (pwm4 output) 3 0 x `0' = normal mode, `1' = special mode (pwm3 output) 2 0 x `0' = normal mode, `1' = special mode (pwm2 output) 1 0 x `0' = normal mode, `1' = special mode (pwm1 output) 0 0 x `0' = normal mode, `1' = special mode (pwm0 output) 0289h port2 tristate register bit reset read write 7 to 0 1 x `0' = output conducting, `1' = output tristate 028a port2 data register bit reset read write 7 to 0 0 port2 data port2 data preliminary data sheet ccz 3005k 70 micronas 028ch port3 mode register bit reset read write 7 0 x `0' = normal mode, `1' = special mode (pwm6 output) 6 0 x `0' = normal mode, `1' = special mode (ir in output) 5 0 x `0' = normal mode, `1' = special mode (ir in ) 4 0 x `0' = normal mode, `1' = special mode (a2 output) 3 0 x `0' = normal mode, `1' = special mode (cc line) 2 0 x `0' = normal mode, `1' = special mode (synctip clamp gate) 1 0 x `0' = normal mode, `1' = special mode (run-in key ) 0 0 x `0' = normal mode, `1' = special mode (average) 028dh port3 tristate register bit reset read write 7 to 0 1 x `0' = output conducting, `1' = output tristate 028eh port3 data register bit reset read write 7 to 0 0 port3 data port3 data 02a8h analog input select and status register bit reset read write (a/d conversion is started) 7 0 `eoc'-flag, if `1': a/d conversion termi- nated x 6 to 3 x x x 2 to 0 0 x no. of analog input pin to convert volt- age from: 0 to 4 for adc0 to adc4 preliminary data sheet ccz 3005k 71 micronas 02a9h a/d converter output value register bit reset read write 7 to 0 x analog value converted from selected adc pin. only valid after `eoc' = `1' x 02d0h i 2 c start cycle without generation of ack (ack = `1') bit reset read write 7 to 0 x x i 2 c-start-data 02d1h i 2 c start cycle with generation of ack (ack = `0') bit reset read write 7 to 0 x x i 2 c-start-data 02d2h i 2 c resume cycle without generation of ack (ack = `1') bit reset read write 7 to 0 x x i 2 c-resume-data (set this byte to $ff for a read access) 02d3h i 2 c resume cycle with generation of ack (ack = `0') bit reset read write 7 to 0 x x i 2 c-resume-data (set this byte to $ff for a read access) 02d4h i 2 c end cycle without generation of ack (ack = `1') bit reset read write 7 to 0 x x i 2 c-terminate-data (set this byte to $ff for a read access) 02d5h i 2 c end cycle with generation of ack (ack = `0') bit reset read write 7 to 0 x x i 2 c-terminate-data (set this byte to $ff for a read access) 02d6h i 2 c/im-bus data from receive-fifo bit reset read write 7 to 0 x received data x preliminary data sheet ccz 3005k 72 micronas 02d7h i 2 c/im-bus status bit reset read write 7 0 x x 6 0 i 2 c or'd ack x 5 0 i 2 c addr ack x 4 0 i 2 c data ack x 3 0 bus busy x 2 0 wr fifo half full x 1 0 rd fifo empty x 0 0 x x 02d8h im-bus start cycle bit reset read write 7 to 0 x x im-bus start (address) data 02d9h im-bus resume cycle bit reset read write 7 to 0 x x im-bus resume data 02dah im-bus end cycle bit reset read write 7 to 0 x x im-bus terminal data 02dbh i 2 c/im-bus prescaler bit reset read write 7 1 x `0' = select im/i 2 c-bus2, `1' = select im/i 2 c-bus1 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 0 x f xtal =n 8 ? bit rate f xtal 8 ? n f xtal 8 ? 128 for n=0: bit rate= for n 0: bit rate= preliminary data sheet ccz 3005k 73 micronas 02f5h ir control and status (bits 0, 1, 3 and 4 are cleared after read) (writing into this register may generate an irq). bit reset read write 7 0 x input trigger edge: `0' = falling, `1' = rising 6 0 ir in -pin level at moment t 2 infrared irq: `0' = disabled, `1' = enabled 5 0 x ir in sample rate: `0' = 85 m s, `1' = 170 m s 4 0 if `1': timer caused interrupt x 3 0 if `1': ir in active start edge found irq source selection: `0': active ir in start edge `1': both ir in samples taken 2 0 ir in level (direct, as if read by standard input port) x 1 0 if `1': both ir in samples taken x 0 0 ir in -pin level at moment t 1 x 02f6h ir sample times register bit reset read write 7 to 4 2 x ir in sample time 2: t 2 (0 to 14, 15 is not allowed) 3 to 0 1 x ir in sample time 1: t 1 (0 to 14, 15 is not allowed) 02feh test register 1 (don't use, reserved for test purposes) bit reset read write 7 to 0 02ffh test register 2 (don't use, reserved for test purposes) bit reset read write 7 to 0 preliminary data sheet ccz 3005k 74 micronas 6. appendix a: closed caption this chapter comprises parts of the standard arecom- mended practice for line 21 data serviceo published as eia-608 by the electronic industries association, wash- ington, usa. the ccz 3005k is intended for the use in conventional analog or digital television receivers. the ccz 3005k is able to decode closed caption transmissions in the ntsc, pal, and secam tv standards (pal and secam standards provided the closed caption data is trans- mitted in the same format as shown in fig. 61 with a bit data rate of 5% of 503 khz). the ic contains a very powerful on-screen display (osd) facility which can handle all of the tv's display functions, as well as dis- playing the closed caption data. the ccd 3000 may be used in set-top decoder boxes with the addition of a sync processor. 6.1. the closed caption standard 6.1.1. data transmission format captions associated with a television program are trans- mitted as an encoded composite data signal during line 21 of field one of the standard ntsc video signal as shown in fig. 61. the signal consists of a clock run-in signal, a start-bit, and 16 bits of data corresponding to two separate bytes of 8 bits each including parity. there- fore, transmission of actual data amounts to 16 bits ev- ery 1/30th of a second or 480 bits per second. this data stream contains encoded information which provides the instructions for display formatting and the characters to be displayed. the clock run-in consists of a seven cycle sinusoidal burst which is frequency and phase locked to the caption data clock rate. the clock run-in signal, whose frequency (32 f h ) is twice that of the data, can be used to provide synchronization for the decoder clock. the clock run-in signal is followed by two data bits at a `0' logical level, then by a logical `1' start-bit. the transmitted data is coded in a non-return-to-zero (nrz) format. all control and alpha-numeric characters utilize the seven-bit code of the us standard code for information interchange (usascii). an eighth bit is added to each character to provide odd parity for error detection. the sequence of identification, control, and character transmission is shown in figs. 62 through 64. each caption transmission is preceded by a preamble control code which consists of a non-printing character and a printing character to form a row address and display col- or code. both characters of the preamble control code and all control codes are always transmitted in a single line 21 and are transmitted twice in succession to ensure correct reception of control information. transmitted caption may be interrupted by mid-caption control codes between two complete words, in order to change display conditions, such as color or italics. at the completion of a caption transmission, an end-of-caption control code is sent. fig. 61: line 21 field 1 data signal format two 7-bit+parity ascii characters (data) start bit blanking level 7 cycles of 503 khz (clock run-in) color burst +40 +20 0 20 40 ire units 33.764 m s 0.53h 3.972 m s (0.06h) 12.91 m s (0.20h) 25 27.452 m s (0.43h) 10.074 m s (0.16h) 51.268 m s 61.342 m s 0.965h +60 preliminary data sheet ccz 3005k 75 micronas sb 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 p p p start bit non-printing control character parity bit printing control character parity bit initialization or mode switching & preamble control mode (each is transmitted twice) caption text (up to 32 characters per row) identification code plus row position, indent & display condition instructions beginning of printed caption fig. 62: caption row preamble form sb 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 p start bit 1st te x t character parity bit 2nd te x t character parity bit sb 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 p p p start bit te x t character parity bit te x t character parity bit last characters prior to mid-row display change display condition instruction code (transmitted twice) fig. 63: mid-caption display condition change format sb 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 p start bit non-printing control character parity bit printing control character parity bit text text control code preliminary data sheet ccz 3005k 76 micronas sb 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 p p p start bit te x t character parity bit te x t character parity bit last characters of caption end of caption control code fig. 64: end of caption and caption transition format sb 1 b 2 b 3 b 4 b 5 b 6 b 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 p start bit non-printing control character parity bit printing control character parity bit end of caption text end of caption control code (transmitted twice) preamble control code next caption (transmitted twice) next caption first text characters the first character of the control code is a non-printing ascii character (000 0000 through 001 1111) followed by a printing character (010 0000 through 111 1110). all characters that are received after a set of valid control codes are interpreted and loaded into memory as print- ing characters. reception of any invalid control code will cause the system to ignore all subsequent character transmissions until it receives a valid control preamble. character codes with bad parity result in an all-ones code being written into memory; this causes display of a box (the delete symbol) in place of the desired charac- ter which, of course, is an error. a valid control code always begins with one of four non- printing ascii control characters dc1, dc2, dc3, or dc4 followed by a printing character code which, when combined, define all the required addressing and dis- play functions. the complete catalog of these control codes is shown on pages 61 through 62. 6.2. closed caption decoder 6.2.1. operating modes there are three modes of operation: caption, text, and tv. the tv mode of operation will disable the display of caption data, allowing the tv video (off-air, vcr, etc.) to be seen in its original form. the text and caption modes black out one or more areas (called aboxeso) on the screen within which caption or text characters are dis- played. in addition, the osd of the ccz may be used to provide customer-specific fade-ins, such as program numbers or names, bars of analog values, etc. 6.2.2. screen format the display area for box(es) and text is 15 rows high by 34 columns wide. vertically, the box area begins on line 43 and is 195 lines high, ending at line 237 (out of 241 full active scan lines in a field). horizontally, the box be- gins at 13.0 m s from the 50% point of the leading edge of sync and is 45.02 m s wide, ending at 58.01 m s. thus, the box area conforms approximately to the standard safe title area for ntsc receivers. text will occupy the middle 32 columns of the box, which are referred to in this document as character positions 1 through 32. 6.2.2.1. text mode in text mode, a black box 15 rows high and 34 columns wide is constantly displayed whenever valid data (see section 6.2.7.) are being processed by the decoder, re- gardless of how many characters, if any, are sent, and regardless of the mode or data channel to which they are addressed. each row of text contains a maximum of 32 characters, leaving no less than a one-column wide box on the left and right of the text. there will never be transparent spaces or transparent rows in text mode. the only transparency will be around the outside of the box. text mode is initiated by receipt of a resume text dis- play command. in text mode, the method of presenting preliminary data sheet ccz 3005k 77 micronas characters depends on whether all 15 rows have been put up on the screen yet. when text mode has just been selected and the specified text memory is empty, the cursor starts at row 1, position 1 and moves down to position 1 on the next row each time a carriage return is received until row 15 is reached. as soon as the first 15 rows of text are on the screen, text mode switches to a scrolling type of presentation. with each subsequent carriage return received, the text on row 1 is erased, text on rows 215 are rolled up one row, and the cursor is moved to position 1 on row 15, which will then be blank. should new displayable characters be received during the time that rows 215 are rolling upwards, the new characters are seen appearing from top to bottom, as each text row is 13 dots high and rolls up at a rate of one dot per frame (thus, a smooth roll-up is completed in 0.433 seconds). if a carriage return is received while text is rolling up, smooth scroll is suspended, causing rows 215 to jump up to their final position so the new carriage return can be processed immediately. characters are always displayed immediately when re- ceived by the decoder. once the cursor reaches the 32nd character position on any row, all subsequent char- acters received prior to a carriage return, preamble ad- dress code, or backspace will be displayed in that posi- tion, replacing any previous character occupying that address. in text mode, the cursor cannot be moved ran- domly around the screen. the cursor automatically moves one column to the right after reception of each character or mid-row code. using any preamble ad- dress code will move the cursor to the indicated indent position on the current row, ignoring row information contained in the address. using a backspace will move the cursor one column to the left, erasing the character or mid-row code occupying that location. (a backspace received when the cursor is in position 1 will be ignored.) using the atext restarto command will erase all charac- ters on the screen and move the cursor to row 1, posi- tion 1. if the reception of data for a row is interrupted by data for the alternate data channel or for caption mode, the dis- play of text will resume from the same cursor position if a aresume text displayo command is received and no preamble address code is given which would move the cursor. a character remains displayed until scrolled off the top of the screen another character is addressed to the same screen location it is erased by a backspace all text is erased simultaneously by receipt of a atext restarto command the user switches data channels (c1/c2) the user switches fields (f1/f2) or by loss of valid data (see section 6.2.7.). in addition, changing the mode select switch to tv will turn off the display of characters and box without erasing data from the decoder memory. 6.2.2.2. caption mode in caption mode, text can appear only on rows 1 to 4 and 12 to 15 of the screen. rows 5 to 11 are never used and will therefore always be transparent. each caption row contains a maximum of 32 characters, and each charac- ter will always be preceded and followed by either anoth- er character or a box no less than one column wide. the caption area will be transparent anywhere that: 1. no standard space character or other character has been addressed and no accompanying box is needed 2. a atransparent spaceo special character has been addressed which does not immediately precede or follow a displayed character. there are three styles of presenting text in caption mode: roll-up, pop-on, and paint-on. character display varies significantly with the style used, but certain rules of character erasure are common to all styles. a character, once displayed, can be erased by addressing another character to the same screen loca- tion or by backspacing over the character from a subse- quent location on the same row. the entire caption dis- play will be erased simultaneously by receipt of an aerase displayed memoryo command, or by the user switching data channels (c1/c2) or fields (f1/f2), or by loss of valid data (see section 6.2.7.), or by commands specific to the type of presentation style used. receipt of an aend of captiono command will cause a displayed caption to become non-displayed (and vice versa) with- out being erased from memory. in addition, changing the mode select switch to tv will turn off the display of char- acters and box without erasing data from the decoder memory. 1. roll-up roll-up style captioning is initiated by using one of three miscellaneous control codes to select the maximum number of rows displayed. a preamble control code will determine the start row or bottom row. the start row must be greater than the number of rows to be scrolled or those rows not in the valid display area will not be dis- played. regardless of the number of active rows selected, the cursor always remains on the start row selected and the text of the four most recently received rows is stored in memory. for convenience, those rows are identified as a, b, c, and d. the first row received when the memory is empty is row a; the second row is row b, the fifth is again row a; etc. if the selected start row =x, each time a carriage return is received, those rows which occupy preliminary data sheet ccz 3005k 78 micronas rows x2, x1 and x roll up one row, whether or not they are in the active display window. the text of the row occupying row x3 is erased, and that now-empty por- tion of memory is addressed to row x ready to accept new text. the cursor is automatically placed at pos. 1. given, for example, that 4row roll-up has been se- lected. the first five rows of text received will display as follows: row 1 (a on row 15) row 1 (a on row 14) row 2 (b on row 15) row 1 (a on row 13) row 2 (b on row 14) row 3 (c on row 15) row 1 (a on row 12) row 2 (b on row 13) row 3 (c on row 14) row 4 (d on row 15) row 2 (b on row 12) row 3 (c on row 13) row 4 (d on row 14) row 5 (a on row 15) if the number of roll-up rows selected were less than four, the display of row 12 or of rows 12 and 13 would be turned off, and the text of those rows would be erased from memory. increasing or decreasing the number of roll-up rows immediately changes the size of the active display window appropriately turning on or off the dis- play of those rows of text occupying rows 12 and 13. as in text mode presentation, the decoder attempts to provide a smooth scroll of displayed rows. each row is 13 dots high and rolls up at a rate of one dot per frame, which means a scroll is completed in 0.433 seconds. should new displayable characters be received during that time, they are seen appearing from top to bottom. if a carriage return is received during the 13-frame roll- up period, smooth scrolling is suspended, causing the rows to jump up immediately to their final position. characters are always displayed immediately when re- ceived by the decoder. once the cursor reaches the 32nd character position on any row, all subsequent char- acters received prior to a carriage return, preamble ad- dress code, or backspace will be displayed in that posi- tion, replacing any previous character occupying that address. the cursor moves automatically one column to the right after each character or mid-row code received. using any preamble address code will move the cursor to the indicated indent position on row 15, ignoring row in- formation contained in the address. using a backspace will move the cursor one column to the left, erasing the character or mid-row code occupying that location. (a backspace received when the cursor is in position 1 will be ignored). the leading box appears when the first displayable char- acter (not a transparent space) or mid-row code is re- ceived on a row, not when preamble address code, if any, is given. a row on which there are no displayable characters or mid-row codes will not display a box, even when rolled up between two rows which do display a box. if the reception of data for a row is interrupted by data for the alternate data channel or for text mode, the display of caption text will resume from the same cursor position if a roll-up caption command is received and no preamble address code is given which would move the cursor. characters remain displayed until scrolled above the top row of the active display window or until one of the stan- dard caption erasure techniques is applied (see section 6.2.2.2.). receipt of a resume caption loading com- mand (for pop-on style) will not affect a roll-up display. receipt of a resume direct captioning command (for paint-on style) will cause all four roll-up rows to be active. receipt of an end of caption command will flip the roll- up captioning into non-displayed memory, also activat- ing all four rows. issuing a roll-up caption command will cause any pop-on or paint-on caption to be erased from displayed memory and/or non-displayed memory. 2. pop-on pop-on style captioning is initiated by receipt of a re- sume caption loading command. subsequent data are loaded into a non-displayed memory and held there until an end of caption command is received, at which point the non-displayed memory becomes the displayed memory and vice versa. (this process is often referred to as flipping memories). an end of caption command forces the decoder into pop-on caption mode if no re- sume caption loading command has been received which would do so. if no preamble address code is received, the cursor will begin at the same screen position where it was left after the previous caption (or at row 1, position 1 when the decoder is first turned on or after a screen erase caused by the user switching data channels or fields or by loss of valid data). preamble address codes can be used to move the cur- sor around the screen in random order to place captions on rows 1 through 15. carriage returns have no effect on cursor location during caption loading. the cursor moves automatically one column to the right after each character or mid-row code received. using preliminary data sheet ccz 3005k 79 micronas a backspace will move the cursor one column to the left, erasing from memory the character or mid-row code occupying that location. (a backspace received when the cursor is in position 1 will be ignored.) once the cur- sor reaches the 32nd character position on any row, all subsequent characters received prior to an end of cap- tion, a preamble address code, or backspace will re- place any previous character at that location. if data reception is interrupted during caption loading by data for the alternate caption channel or for text mode, caption loading will resume at the same cursor position if a resume caption loading command is received and no preamble address code is given that would move the cursor. characters remain in non-displayed memory until an end of caption command flips memories. the caption will be erased without being displayed upon receipt of an erase non-displayed memory command or a roll-up caption command, or if the user switches data channels or fields, or upon the loss of valid data. a pop-on caption, once displayed, remains displayed until one of the standard caption erasure techniques is applied (see section 6.2.2.2.) or until a roll-up caption command is received. characters within a displayed pop-on caption can be replaced using the resume direct captioning command and paint-on style techniques. 3. paint-on paint-on style captioning is initiated by receipt of a re- sume direct captioning command. subsequent data are addressed immediately to displayed memory without need for an end of caption command. if no preamble address code is received, the cursor will begin at the same screen position where it was left after the previous caption (or at row 1, position 1 when the de- coder is first turned on or after a screen erase caused by the user switching data channels or fields or by loss of valid data). preamble address codes can be used to move the cur- sor around the screen in random order to display cap- tions on rows 1 through 15. carriage returns have no ef- fect on cursor location during direct captioning. the cursor moves automatically one column to the right after each character or mid-row code received. using a backspace will move the cursor one column to the left, erasing the character or mid-row code occupying that location. (a backspace received when the cursor is in position 1 will be ignored.) once the cursor reaches the 32nd character position on any row, all subsequent char- acters received prior to a preamble address code or backspace will be displayed in that position, replacing any previous character occupying that address. if the reception of data is interrupted during direct cap- tioning by data for the alternate caption channel or for text mode, the display of caption text will resume at the same cursor position if a aresume direct captioningo command is received and no preamble address code is given which would move the cursor. characters remain displayed until one of the standard caption erasure techniques is applied (see section 6.2.2.2.) or until a aroll-up captiono command is re- ceived. an aend of captiono command leaves a paint-on caption fully intact in non-displayed memory. in other words, a paint-on style caption behaves precisely like a pop-on style caption which has been displayed. 6.2.3. presentation format in analyzing the presentation of characters, it is conve- nient to think in terms of a non-visible cursor which marks the screen position at which the next event in a given mode and data channel will occur. the decoder re- members the cursor position for each mode even when data are received for a different address in the alternate mode or data channel. 6.2.4. character format characters are to be displayed on the screen in a dot matrix format. each character will be displayed within a character acello which is the height and width of a single row and column. each cell is 13 dots high by 8 dots wide. vertically, each dot is to be one pair of interlaced scan lines. within a field, this design will make a character cell 13 scan lines high, but within a frame each cell will be 26 scan lines high. (the lines from each field are like-numbered pairs). there are no scan lines between character rows. in 525 standards the vertical dots are said to be in dot rows, with the topmost dot row being numbered dot row 0 (zero) and the bottommost being dot row 12. dot rows 0 and 12 will always be blank, providing vertical spacing between characters. an underline, if used (see section 6.2.5.), will be shown on dot row 11. dot rows 1 through 11 are for the displayed character. the horizontal dots of the cell are numbered from dot 0 (zero) on the left to dot 7 on the right. dot 7 on every dot row will always be blank, except on dot row 11 when the underline attribute is assigned. this method provides horizontal spacing between characters while connect- ing an underline from cell to cell. preliminary data sheet ccz 3005k 80 micronas table 61: special characters (the values are hexa- decimal numbers) data channel character 1 2 11 30 19 30 ? 11 31 19 31 degree sign 11 32 19 32 1/2 11 33 19 33 inverse query 11 34 19 34 ? (trade mark) 11 35 19 35 cents sign 11 36 19 36 pounds sign 11 37 19 37 music note 11 38 19 38 lower-case a with grave ac- cent 11 39 19 39 transparent space 11 3a 19 3a lower-case e with grave ac- cent 11 3b 19 3b lower-case a with circumflex 11 3c 19 3c lower-case e with circumflex 11 3d 19 3d lower-case i with circumflex 11 3e 19 3e lower-case o with circumflex 11 3f 19 3f lower-case u with circumflex note: this is not a complete list of special characters. 6.2.5. character attributes a character may have any or all of four attributes: color, italics, underline and flash. all of these attributes are set by control codes included in the received data. an attrib- ute will remain in effect until another control code is re- ceived or until the end of the row is reached. each row begins with a control code which sets the color and un- derline attributes. (white non-underlined is the default if no preamble address code is received before the first character on an empty row). attributes are not affected by transparent spaces within a row. all mid-row codes and the aflash ono command are spacing attributes which appear in the display just as if a standard space (20h) had been received. preamble address codes are non-spacing and will not alter any at- tributes when used to position the cursor in the midst of a row of characters. the color attribute has the highest priority and can only be changed by the mid-row code of another color. italics has the next highest priority. if characters with both color and italics are desired, the italics mid-row code must follow the color assignment. any color mid- row code will turn off italics. if the least significant bit of a preamble address code or of a color or italics mid-row code is a 1 (high), underlin- ing is turned on. if that bit is a 0 (low), underlining is off. the flash attribute is transmitted as a miscellaneous control code. the flash on command will not alter the status of the color, italics, or underline attributes. howev- er, any color or italics mid-row code will turn off flash. thus, for example, if a red, italicized, underlined, flash- ing character is desired, the attributes must be received in the following order: a red mid-row or preamble ad- dress code, an italics mid-row code with underline bit, and the flash on command. the character will then be preceded by three spaces (two if red was assigned via a preamble address code). the available colors are white, green, blue, cyan, red, yellow, and magenta. in all cases, the background is black. a character with italics will have a two-dot slant to the right over the vertical range of the character as defined above. an underline attribute will draw an underline beneath a character in the same color as the character. the under- line resides on dot row 11, one dot row below the lowest dot of a character. it covers the entire width of a column. a flash attribute will blank the display of a character for 0.25 seconds once per second. 6.2.6. control codes there are three different types of control codes used to identify the format, location, attributes, and display of characters: preamble address codes, mid-row codes, and miscellaneous control codes. each control code consists of a pair of bytes which are always transmitted together in a single field of line 21 and which are normally transmitted twice in succession to help ensure correct reception of the control instruc- tions. the first of the control code bytes is a non-printing character in the range 10h to 1fh. the second byte is always a printing character in the range 20h to 7fh. any such control code pair received which has not been as- signed a function is ignored. if the non-printing character in the pair is in the range 00h to 0fh, that character alone will be ignored and the second character will be treated normally. if the second byte of a control code pair does not contain odd parity, the pair is ignored. the redundant transmis- preliminary data sheet ccz 3005k 81 micronas sion of the pair will be the instruction upon which the de- coder acts. if the first byte of the first transmission of a control code pair fails the parity check, then that byte is inserted into the currently active memory as a block character (7fh) followed by whatever the second byte is. again, the re- dundant transmission of the pair will be the controlling instruction. if the first transmission of a control code pair passes par- ity, it is acted upon immediately. if the next frame con- tains a perfect repeat of the same pair, the redundant code is ignored. if, however, the next frame contains a different but also valid control code pair, this pair, too, will be acted upon (and the decoder will expect a repeat of this second pair in the next frame). if the first byte of the expected redundant control code pair fails the parity check and the second byte is identical to the second byte in the immediately preceding pair, then the expected re- dundant code is ignored. if there are printing characters in place of the redundant code, they will be processed normally. the first byte of every control code pair indicates the data channel (c1/c2) to which the command applies. if bit 3 of this byte is a a0o (xxxx0xxx), data channel 1 is indi- cated. if bit 3 is a a1o (xxxx1xxx), data channel 2 is indi- cated. control codes which do not match the data chan- nel switch position selected by the user, and all subsequent data related to that control code, are ig- nored by the decoder. table 62: miscellaneous control codes (the values are hexadecimal numbers) data channel mnemonic command description 1 2 14 20 1c 20 rcl resume caption loading 14 21 1c 21 bs backspace 14 22 1c 22 reserved 14 23 1c 23 reserved 14 24 1c 24 der delete to end of row 14 25 1c 25 ru2 roll-up captions 2 rows 14 26 1c 26 ru3 roll-up captions 3 rows 14 27 1c 27 ru4 roll-up captions 4 rows 14 28 1c 28 fon flash on 14 29 1c 29 rdc resume direct captioning 14 2a 1c 2a tr text restart 14 2b 1c 2b rtd resume text display 14 2c 1c 2c edm erase displayed memory 14 2d 1c 2d cr carriage return 14 2e 1c 2e enm erase non-displayed memory 14 2f 1c 2f eoc end of caption (flip memories) 17 21 1f 21 to1 top offset 1 column 17 22 1f 22 to2 top offset 2 columns 17 23 1f 23 to3 top offset 3 columns preliminary data sheet ccz 3005k 82 micronas table 63: mid-row codes data channel attribute description 1 2 11 20 19 20 white 11 21 19 21 white underline 11 22 19 22 green 11 23 19 23 green underline 11 24 19 24 blue 11 25 19 25 blue underline 11 26 19 26 cyan 11 27 19 27 cyan underline 11 28 19 28 red 11 29 19 29 red underline 11 2a 19 2a yellow 11 2b 19 2b yellow underline 11 2c 19 2c magenta 11 2d 19 2d magenta underline 11 2e 19 2e italics 11 2f 19 2f italics underline preliminary data sheet ccz 3005k 83 micronas table 64: standard telecaption character set lsb msb 2 3 4 5 6 7 0 0 @ p p 1 ! 1 a q a q 2 o 2 b r b r 3 # 3 c s c s 4 $ 4 d t d t 5 % 5 e u e u 6 & 6 f v f v 7 ' 7 g w g w 8 ( 8 h x h x 9 ) 9 i y i y a : j z j z b + ; k [ k ? c ' < l l d = m ] m ? e . > n n ? f / ? o o preliminary data sheet ccz 3005k 84 micronas table 65: preamble address codes (the values are hexadecimal numbers) row no. first byte of code pair 1 2 3 4 12 13 14 15 data channel 1 11 11 12 12 13 13 14 14 data channel 2 19 19 1a 1a 1b 1b 1c 1c second byte of code pair white 40 60 40 60 40 60 40 60 white underline 41 61 41 61 41 61 41 61 green 42 62 42 62 42 62 42 62 green underline 43 63 43 63 43 63 43 63 blue 44 64 44 64 44 64 44 64 blue underline 45 65 45 65 45 65 45 65 cyan 46 66 46 66 46 66 46 66 cyan underline 47 67 47 67 47 67 47 67 red 48 68 48 68 48 68 48 68 red underline 49 69 49 69 49 69 49 69 yellow 4a 6a 4a 6a 4a 6a 4a 6a yellow underline 4b 6b 4b 6b 4b 6b 4b 6b magenta 4c 6c 4c 6c 4c 6c 4c 6c magenta underline 4d 6d 4d 6d 4d 6d 4d 6d white italics 4e 6e 4e 6e 4e 6e 4e 6e white italics underline 4f 6f 4f 6f 4f 6f 4f 6f indent 0 50 70 50 70 50 70 50 70 indent 0 underline 51 71 51 71 51 71 51 71 indent 4 52 72 52 72 52 72 52 72 indent 4 underline 53 73 53 73 53 73 53 73 indent 8 54 74 54 74 54 74 54 74 indent 8 underline 55 75 55 75 55 75 55 75 indent 12 56 76 56 76 56 76 56 76 indent 12 underline 57 77 57 77 57 77 57 77 indent 16 58 78 58 78 58 78 58 78 indent 16 underline 59 79 59 79 59 79 59 79 indent 20 5a 7a 5a 7a 5a 7a 5a 7a indent 20 underline 5b 7b 5b 7b 5b 7b 5b 7b indent 24 5c 7c 5c 7c 5c 7c 5c 7c indent 24 underline 5d 7d 5d 7d 5d 7d 5d 7d indent 28 5e 7e 5e 7e 5e 7e 5e 7e indent 28 underline 5f 7f 5f 7f 5f 7f 5f 7f note: all indent codes (second byte equals 50h5fh, 70h7fh) assign white as the color attribute. preliminary data sheet ccz 3005k 85 micronas 6.2.7. data rejection the decoder tends to reject data for three reasons: the data are invalid, they are signalled for the data channel not selected by the user, or they are in the line 21 field not selected by the user. invalid data are data which fail to pass a check for odd parity or data which, having passed the parity check, are assigned no function. the effect of invalid data in control codes is covered in sec- tion 6.2.6. other data which fail parity are always dis- played in the current mode (i.e. the same mode as the preceding non-null byte) as block characters (7fh). a parity error in 45 successive frames will disable the vid- eo display and erase all memories (see section 6.2.8.). data rejected for any other reason are ignored and, therefore, lost. 6.2.8. automatic display enable/disable the decoder will automatically enable and disable the display of box and text in response to the presence or absence of valid data on line 21. 6.2.8.1. enable logic and timing the minimum time for the display to be enabled while disabled is 15 frames. when the decoder is first turned on, or after the display has been disabled, it will not be enabled until 15 consecutive frames have been received in which both data bytes pass the check for odd parity. if, while accumulating the 15 frames, a frame occurs in which no data is detected or in which one or more data bytes have even parity, the count of consecutive frames will be reset to zero. the data contained in the 15 frames counted to enable the display are preserved and will be displayed appropriately immediately after the 15th frame. 6.2.8.2. disable logic and timing the minimum time for the display to be disabled while enabled is 45 frames. after the display has been enabled, it will not be disabled until 45 consecutive frames have been received in which no data are detected or in which at least one data byte has even parity. if, while accumulating the 45 frames, a frame occurs in which both data bytes have odd parity, the count of consecutive frames will be reset to zero. preliminary data sheet ccz 3005k 86 micronas 7. appendix b: pin configuration of cpga package 100 104 106 108 110 114 116 118 120 122 124 126 128 1 97 99 102 105 109 112 113 119 121 125 129 130 132 5 95 98 101 103 107 111 115 117 123 127 131 2 3 9 93 94 96 4611 75 69 68 65 61 57 51 49 45 41 37 35 32 29 71 66 64 63 59 55 53 47 46 43 39 36 33 31 67 62 60 58 56 54 52 50 48 44 42 40 38 34 89 90 92 7813 87 88 91 10 12 15 85 86 84 16 14 17 83 80 82 18 20 19 81 78 76 25 22 21 79 74 73 26 24 23 77 72 70 30 28 27 a b c d e f g h j k l m n p a b c d e f g h j k l m n p 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view fig. 71: pinning of emu ccz 3005k in 132-pin ceramic package grid array (cpga132f ) preliminary data sheet ccz 3005k 87 micronas 7.1. pin connections in cpga132f package bond pin symbol bond pin symbol bond pin symbol bond pin symbol 1 a1 nc 34 p1 nc 67 p14 nc 100 a14 nc 2 c3 nc 35 m3 p13 68 m12 p26 101 c12 p02 3 c2 gnda 36 n3 nc 69 m13 nc 102 b12 nc 4 d3 v supa 37 m4 p14 70 l12 p27 103 c11 p03 5 b1 half-video 38 p2 nc 71 n14 nc 104 a13 nc 6 d2 b out 39 n4 reset ? 72 l13 p30 105 b11 p04/v osd 7 e3 nc 40 p3 nc 73 k12 nc 106 a12 nc 8 e2 g out 41 m5 xtal1 74 k13 p31 107 c10 p05/h osd 9 c1 nc 42 p4 nc 75 m14 nc 108 a11 nc 10 f3 r out 43 n5 xtal2 76 j12 p32 109 b10 p06 11 d1 fast blank 44 p5 nc 77 l14 nc 110 a10 nc 12 f2 h sync1 45 m6 gnd 78 j13 p33 111 c9 p07 13 e1 v sync 46 n6 nc 79 k14 a0 112 b9 d0 ? 14 g2 emu 47 n7 v sup 80 h13 a1 113 b8 d1 ? 15 f1 r/w 48 p6 test 81 j14 a2 114 a9 d2 ? 16 g3 ce 49 m7 a8 82 h12 a3 115 c8 d3 ? 17 g1 f 2 50 p7 a9 83 h14 a4 116 a8 d4 ? 18 h3 nmi 51 m8 a10 84 g12 a5 117 c7 d5 ? 19 h1 f 2 cpu 52 p8 a11 85 g14 a6 118 a7 d6 ? 20 h2 dma 53 n8 a12 86 g13 a7 119 b7 d7 ? 21 j1 nmi cpu 54 p9 a13 87 f14 irq 120 a6 nc 22 j2 f 2 out 55 n9 a14 88 f13 p34 121 b6 nc 23 k1 reset cpu 56 p10 a15 89 e14 nc 122 a5 video in 24 k2 sync cpu 57 m9 p20 90 e13 p35 123 c6 slicer cap. 25 j3 ccline 58 p11 p21 91 f12 nc 124 a4 gnd (porqtest) 26 k3 synctip clamp gate 59 n10 p22 92 e12 p36 125 b5 adc 0 27 l1 run-in key 60 p12 nc 93 d14 nc 126 a3 adc 1 28 l2 p10 61 m10 p23 94 d13 p37/pwm6 127 c5 adc 2 29 m1 nc 62 p13 nc 95 c14 nc 128 a2 nc 30 l3 p11 63 n11 p24 96 d12 p00 129 b4 adc 3 31 n1 nc 64 n12 nc 97 b14 nc 130 b3 nc 32 m2 p12 65 m11 p25 98 c13 p01 131 c4 adc 4 33 n2 nc 66 n13 nc 99 b13 nc 132 b2 nc standard pin additional emu pin nc ? input bidirectional output direction programmable preliminary data sheet ccz 3005k 88 micronas 8. data sheet history 1. preliminary data sheet: accz 3005k central control unito, june 28, 2000, 6251-471-1pd. first release of the preliminary data sheet. micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-471-1pd all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. by this publication, micronas gmbh does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. |
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